If you're using an AD985x style DDS chip to generate a clock, get yourself a decent quality, high speed LVPECL/LVDS oscillator and use it as the reference clock. A 155.52MHz SONET oscillator is probably up your alley - just make sure it's an overtone or high freq. fundamental part, try to avoid ones which use analog multiplication or PLLs inside. If you're not sure, contact the vendor.
The AD985x has a PLL inside which lets you clock it at, say, 200MHz using a lower frequency source - but that PLL uses a ring VCO which doesn't have the best phase noise.
Also, design a decent lowpass filter for the DDS output, such that at the highest output frequency (24.576M) there's a decent amount of rejection of the nyquist spur at (155.52MHz-24.576M). Feed the filtered output into your comparator to get your desired clock. Passband ripple in the filter doesn't matter that much so I usually throw a chebyshev at a design like this.
This is standard practice for generating high quality RF, it might be overkill for audio - of course, there probably isn't such a thing 😉
The AD985x has a PLL inside which lets you clock it at, say, 200MHz using a lower frequency source - but that PLL uses a ring VCO which doesn't have the best phase noise.
Also, design a decent lowpass filter for the DDS output, such that at the highest output frequency (24.576M) there's a decent amount of rejection of the nyquist spur at (155.52MHz-24.576M). Feed the filtered output into your comparator to get your desired clock. Passband ripple in the filter doesn't matter that much so I usually throw a chebyshev at a design like this.
This is standard practice for generating high quality RF, it might be overkill for audio - of course, there probably isn't such a thing 😉
what about use crystal with freq you want to use and use diode to switch the right crystal you need like band switch in old transceiver. I am very sure the crystal based osc will have lower jitter than the best PLL you can design.
DDS if you not afraid about uC programming its will good enough but still I stand for multi crystal oscillator.
DDS if you not afraid about uC programming its will good enough but still I stand for multi crystal oscillator.
The DDS method lets you make a DAC with decent clock recovery that accepts a wide sample rate, not just specific sample rate ranges (44.1/related +-100ppm, 48/releated +-100ppm, etc) that you'd get with a dual-VCXO PLL system.
Not that you'd ever need that.
Not that you'd ever need that.
Is this something you have built and tested? could you post a block diagram. There is always an static frequency error + drift without an analog loop or voltage controlled osc to track the data stream.
Not for audio, but I've done similar systems for RF.
The whole system can be realized 100% digitally. The DDS replaces the VCO, and you can use digital sampling for your phase detector. You'll end up with an ADPLL (all-digital PLL) when you're done.
I'd use a CPLD (XC9500XL or similar family) as a phase detector. Divide the SPDIF receiver clock and the DDS clock down to sensible values (a couple hundred Hz each) and feed the divided output into a PFD circuit. Design your PFD so it gives you two separate signals, phase error and polarity.
Using a microcontroller with a 16 bit or better timer, measure the length of the PFD pulse, and take note of the polarity while you're at it. You've captured your phase error.
Using that error, do the appropriate math and update the DDS with a new tuning word. As for that math, I've posted the equations for a software controlled PLL using PI control in this discussion:
DIYHiFi.org • View topic - Microcontroller based PLL
It probably can't hurt to use a second timer in the microcontroller to count divided SPDIF clocks, to give you a basic idea of the input sample rate. This way you can put the DDS at an approximate frequency first, then use the PLL to pull it in - this will let you lock faster.
- Status
- Not open for further replies.