Hi James,
Your issue is most probably noise pick up due to the small case you use. Eliminating the noise with snubbers may help but you can also experiment with different layout to see if it betters. Your wifi and computer are also noise generators.
A ground loop will easily pick up noise so you might check the grounds.
Nice explanation from Clarke. I have always found centre tapped half brige better sounding than full bridge. You also halve the amount of diodes and thus noise generators.
Current runs from - to + so eliminating the diodes at that spot makes for lower impedance.
Another way to get rid of diode noise is to use tube rectifiers, they do not have the noise issues diodes portray. There are tube rectifiers for low voltage use made in the past.
Regards,
Your issue is most probably noise pick up due to the small case you use. Eliminating the noise with snubbers may help but you can also experiment with different layout to see if it betters. Your wifi and computer are also noise generators.
A ground loop will easily pick up noise so you might check the grounds.
Nice explanation from Clarke. I have always found centre tapped half brige better sounding than full bridge. You also halve the amount of diodes and thus noise generators.
Current runs from - to + so eliminating the diodes at that spot makes for lower impedance.
Another way to get rid of diode noise is to use tube rectifiers, they do not have the noise issues diodes portray. There are tube rectifiers for low voltage use made in the past.
Regards,
Just a basic question from dddac1794_nos_ver30.pdf while do not like to read all entries 😱
Question:
1) Is the Analog part of the DAC really with 8 Volts powered, as seen in the pdf?
2) Is the BCK clock coming from WAVEIO or SPDIF an always continuous clock, no means of burst related data clock?
cheers
Hp
Question:
1) Is the Analog part of the DAC really with 8 Volts powered, as seen in the pdf?
2) Is the BCK clock coming from WAVEIO or SPDIF an always continuous clock, no means of burst related data clock?
cheers
Hp
Just my reading on the Ti spec-sheet:
1) while BCK & SCK are connected together, while SCK is the jitter sensitive master clock 😀
2) absolute max analog power values is 6.5 Volt specified... 😱
Hp
If I remember correctly what I've saw during reading the whole lot (it's some time ago), you will find the answers why it's done this way! (I am sure about the explanation for the higher than specified voltage)
So if you really want to know, I would advise you to start reading the whole lot...
So if you really want to know, I would advise you to start reading the whole lot...
Hi HPW,
....the "whole lot" this time for you fortunately means just reading Doedes development story on his website: dddac.com
You can read it in 20 minutes....
Ed
....the "whole lot" this time for you fortunately means just reading Doedes development story on his website: dddac.com
You can read it in 20 minutes....
Ed
OK reading now:
1) A logical thought was to reduce the System Clock (SCK) by 4 and the whole thing must be ok than. And then the final spark.... BCK is actually 1/4 of SCK, so why not connect BCK to the SCK input? This is against ALL LOGIC and seems to be definitively not supported by the datasheet...... BUT ..... it works perfectly 🙂
2) The datasheet tells us, that the maximum Vcc (analog supply) is 6,5 Volt. Oh really? This is just a current source, hard to believe after my experience with the TDA1543, that this is really the maximum. This is the most easy test... Play music, connect the VCC to a LAB power supply and slowly increase the supply voltage. Measure the supply current and wait till it SMOKES 🙂 Believe it or not, the Chip worked fine till 10 Volts. It smoked at 11 Volts. I also found out by several test, that there was a kind of maximum, in such way, that there was no improvement in headroom, which was like round 8,5 Volt. Therefore I decided that 8 volt would be a great compromise.
Cheers
Hp
A simple question.
I have 8 Schottky rectifier diodes, and wonder if it's any point in put together two full wave rectifier bridges in my coming choke psu setup ( clclc ). I was thinking of paralleling the bridges, or is it better to set them up in series ? Pros and cons ?
Have been reading alot about two vs one bridge, but still confused.
I have 8 Schottky rectifier diodes, and wonder if it's any point in put together two full wave rectifier bridges in my coming choke psu setup ( clclc ). I was thinking of paralleling the bridges, or is it better to set them up in series ? Pros and cons ?
Have been reading alot about two vs one bridge, but still confused.
I never paid attention to this. Since I bought my boards in two batches, one is the old style, version 2.0, and the three others are of the newer type version 3.0, I’ve probably always been playing with a delay mismatch..
Bugger, that means the whole stack needs to come apart again..
I do not want rain on your disassembling party Stijn, but this wil do nothing for you. Timing is only determined by the clock BCK and there are no differences between the boards in this aspect. The clock just transfers a one or zero in the dac register at the BCK Flank. Therefore you need a stable zero or one at that point. in the beginning I was not sure, so I took the 1k value. It turned out that there was no need for this extra delay, so I went back to 3x100 ohm. basically on the different boards there is only an effect how early the DATA bit is available to be clocked. the BCK is key here, not the DATA bit
The fact that the new blue board setup with the extra half clock delay lines and for most extra buffering of the I2S bus might proof to help a bit SQ is another thing. Although you might want to think about the above. I believe it is very unlikely it has to do with when the data bit is available. You cannot be too early. Clock is clock. The delay will have nothing to do with it. As said, most likely the buffering does it.
The fact that the new blue board setup with the extra half clock delay lines and for most extra buffering of the I2S bus might proof to help a bit SQ is another thing. Although you might want to think about the above. I believe it is very unlikely it has to do with when the data bit is available. You cannot be too early. Clock is clock. The delay will have nothing to do with it. As said, most likely the buffering does it.
Can you first just strip to two identical boards and audition. You may get best sound following James < less may be more > route. And try something like a resistor on each output into a copper Jensen cap and out on its own.
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I defer to Doede's much greater knowledge than mine but from my experience and a friend's there is more to it than this. When we both used mixed 1k and 100r boards on our four decker standard builds, we both have often remarked that low bit rate sounds 'better' than it should while hi res sounded worse than red book and red book did not sound consistently better than 128kb. (better in some respects not in others). I also remarked on this Forum and to my friend that going from the four boarder to a one boarder, before I started modding psus, super regulators, ccs and reclockers, was much less of a jump back than I expected and it seemed to be doing somethings better than my four boarder.
On reassembling a two board bog standard unit with matching 100r resistors, the hierarchy from low bit to high bit in terms of SQ is correctly displayed and the two board with matched resistors sounds more coherent than my four decker with mixed resistors ever did.
So, I'm not proffering an explanation but I don't believe we have all the answers either!
Doede, I totally trust your opinion on the matter, so I'll leave it for now.
I'm sure I'll take it apart sooner or later again anyway
Thanks,
I can't see a grey area
no 1/2 clock cycle lc you need 1k on data
with 1/2 clock cycle lc less than 100 ohm on data
a mix of 1k and 100 ohms is neither one nor the other
The difference in Sq is unmistakable
no 1/2 clock cycle lc you need 1k on data
with 1/2 clock cycle lc less than 100 ohm on data
a mix of 1k and 100 ohms is neither one nor the other
The difference in Sq is unmistakable
we are mixing things here. I found out, you do not Need the 1k to introduce another 10ns delay for the Data bit to be ready for clocking the data bit into the dac register. That is fact, 100 Ohm is ok. So mixing is no issue. See it like this, the clock will not know if the data bit will exist for another 10ns or not when it is clocking this bit inot the dac.
anything else is another case, as this is Audio. To be very sure do a A-B with two DACs with a 100 and 1k in dataline and see if you can tell the difference. I would be extremely surprised if you can.
anything else is another case, as this is Audio. To be very sure do a A-B with two DACs with a 100 and 1k in dataline and see if you can tell the difference. I would be extremely surprised if you can.
doede,
As a noob here in this electronic land, would the 1k affect signal rise time compared to the 100R? I know that's it's 1's and 0's, but combination ed with any capacitance etc of the in out and the trace, could that be causing a change in the signal propagation in some way?
just that there guys seem very sure there is a difference.
o
Interested to know your thoughts even though I may be way off base.
Laters,
Drew.
As a noob here in this electronic land, would the 1k affect signal rise time compared to the 100R? I know that's it's 1's and 0's, but combination ed with any capacitance etc of the in out and the trace, could that be causing a change in the signal propagation in some way?
just that there guys seem very sure there is a difference.
o
Interested to know your thoughts even though I may be way off base.
Laters,
Drew.
I'm running out of things to do.. 😉
I moved the power button of BBB to the front panel and hooked up a battery to the BBB in the hope of preventing any accidents.
Other recent additions:
- OTTO-II IS2 switch
- S03 reclocking/isolation board
- R-Core 18V 120VA transformer
- & the CCS's of course
I've very pleased with the sonic improvements.
I moved the power button of BBB to the front panel and hooked up a battery to the BBB in the hope of preventing any accidents.
Other recent additions:
- OTTO-II IS2 switch
- S03 reclocking/isolation board
- R-Core 18V 120VA transformer
- & the CCS's of course
I've very pleased with the sonic improvements.
Well, I did just an analyze of your TTL & propagation delays... 😀
IMHO there is an design issue in combination with the synchronous shift registers.
1. The data propagation time on the shift registers is about 5-12 ns (dependent on the load)
2. From the above means, your data stream from the shift register to the DAC is delayed
3. The DAC BCK is equal as on the ADC and triggered by positive clock edge
4. The DAC requires referenced to the BCK, a data setup and hold time of 10 ns (see TI spec's)
5. means setup time: data have to be 10ns ready before BCK rise
6. means hold time: data have to be 10ns stable after BCK rise
7. In other words your data from the shift registers alters in the same time as the BCK edge on the DAC.
Old man knowledge using resistor in TTL logic as a compensation delay is equal as "lost in the dark"
Or I just miss something...
Hp
Yes, you missed the fact that theory not always matched practice 😀
Of course I am fully aware of this, even being an old man. The funny thing however was that both ( with and without half cycle delay ) works perfectly. And the change of data signal is indeed long enough after clock rise to make it work.
datasheets normally are very conservative. Same goes for the analog suppy voltage of Max 6,5 volts 😉
I am not know for plain datasheet implementations, which makes the hobby so interesting and the results so awesome (some times), please don't mix that with design issues or judging my abilities as lost in the dark.
But no hard feelings, I have had harsher comments on my designs in the past, which went very personal. Not sure why, live and let hobby I would say....