Hi all...
I want the DAC im designing to support 24bit, but i want to also use the TAS3001 (kinda DSP) which only supports 20bit.
Im not worried about loosing the 4bits of audio data.
If i make the SPDIF recv (DIR1703) output in "24bit, MSB first, left justifed", and put the TAS3001 in "20bit, MSB first, left justified", will it work the way i want?
As in the TAS3001 just ignoring the 4 least significant bits?
If not, is there another way i can do this?
Thanks.
I want the DAC im designing to support 24bit, but i want to also use the TAS3001 (kinda DSP) which only supports 20bit.
Im not worried about loosing the 4bits of audio data.
If i make the SPDIF recv (DIR1703) output in "24bit, MSB first, left justifed", and put the TAS3001 in "20bit, MSB first, left justified", will it work the way i want?
As in the TAS3001 just ignoring the 4 least significant bits?
If not, is there another way i can do this?
Thanks.
Sonic Amputation
As long as you are using a left justified MSB 1st or IIS data format, the TAS3001 will just truncate the four extra LSBs and it should work. If you're using a right justified format, there will be problems.
Sonically it would be desirable to add some dither to the twentieth bit, rather than just truncating the LSBs. Unfortunately, the TAS3001 can't generate dither. Perhaps there's a small chance that you can change the dither of your source?
I'm also presently laying out a board to play with TI's DAP chips.
I'm dealing with this issue in two separate ways:
1st: I'm laying out the board so that it will accommodate both the TAS3001 and the upcoming TAS3103 (which supports up to 32bit word lengths). That way I can simply replace the TAS3001 as soon as they start sampling the TAS3103.
2nd: I'm using an AD1896 ASRC before the input to the DAP. This chip includes the ability to add dither when truncating the word length. (Of course its main benifits are being able to change sample rates and reduce jitter by reclocking the signal).
Regards,
Brian.
As long as you are using a left justified MSB 1st or IIS data format, the TAS3001 will just truncate the four extra LSBs and it should work. If you're using a right justified format, there will be problems.
Sonically it would be desirable to add some dither to the twentieth bit, rather than just truncating the LSBs. Unfortunately, the TAS3001 can't generate dither. Perhaps there's a small chance that you can change the dither of your source?
I'm also presently laying out a board to play with TI's DAP chips.
I'm dealing with this issue in two separate ways:
1st: I'm laying out the board so that it will accommodate both the TAS3001 and the upcoming TAS3103 (which supports up to 32bit word lengths). That way I can simply replace the TAS3001 as soon as they start sampling the TAS3103.
2nd: I'm using an AD1896 ASRC before the input to the DAP. This chip includes the ability to add dither when truncating the word length. (Of course its main benifits are being able to change sample rates and reduce jitter by reclocking the signal).
Regards,
Brian.
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