Yes. I initially modeled it with LSK489A with standing current below the lowest possible Idss, and 3k9 was the optimal value of load resistors for it. I did not update them after replacing the input device with JFE2140 and increasing the current to ~4mA per side.
Not much, just a little.
If they draw 9.6 mA together, then the voltage drop across the 46 ohm source resistor must be about 0.44 V.
At -0.44 V gate-source voltage, the current is far below 4.8 mA according to this Toshiba graph, at least at 10 V drain-source voltage.
The value of 46 ohm is what I need for R4 in the LTspice sim.
In 'real life' - ie. actually measuring the built circuit - the value of R4 is 4R4 and the Source voltage I get ... leads to a combined current of about 9.6ma. Drain-Source voltage is about 8v.
With 4.4 ohm and about 30 mS per FET (transconductance at 4.8 mA from a Toshiba datasheet graph), only 20.886 % of the input AC voltage will drop across the resistor, so you can only get about 20 % of capacitance reduction. The remaining capacitance is then 48 pF when you connect C3 to the resistor, 50.4 pF when you don't.
This seems to work.
I had to introduce compensation to make it stable.
AC analysis shows a 2dB peak at 3.2MHz. It's a good thing that there will be a passive low-pass filter implementing the 75us RIAA pole after this stage.
I had to introduce compensation to make it stable.
AC analysis shows a 2dB peak at 3.2MHz. It's a good thing that there will be a passive low-pass filter implementing the 75us RIAA pole after this stage.
Thanks, Marcel. 👍
So ... not really worth doing. 🙁
But I'm confused by sk's post here:
How can I do what he says ... ie. "eliminate the capacitance of the input device altogether"? What change in my circuit do I need to make, to achieve this?
There are two in parallel, so you should draw a 92 ohm loadline to find the current per JFET. Hence my estimate of 2 mA for an average IDSS.
stratokaster83 assumes perfect voltage follower behaviour from gate to source. You cannot completely achieve that, but you could get a lot closer by replacing the FETs with some multistage negative feedback circuit (for example a Sziklai pair with a JFET as its first stage and a current source or resistor for biasing it) or by using a much larger source resistor - which would reduce the transconductance, which is unacceptable according to one of your earlier posts.