Andy, tying the drains of the lower devices to the emitter of the cascode removes the Miller effect. However, you still have the Ciss of the device itself to deal with, which in the case of LSK170 is pretty substantial (~60pF, IIRC).
But if you tie the base (or the gate) of the upper device to the source of the lower device, you’re preventing any voltage variation from developing between the drain and the source of the input device(s), which not only mitigates the Miller effect, but also effectively eliminates the capacitance of the input device altogether.
The attachment may or may not be relevant to your discussion. It's relevant if you are worried about Miller effect and the closed-loop input capacitance of the preamplifier.
This LEDs works simply like a low voltage zener, the function is to translate AC input voltage from FET gate-source to cascode base-emitter. This procedure ensures that the AC voltage at the drain of the field-effect transistor is equal to the input voltage at its gate, i.e. the current does not flow into the input capacitance of the field-effect transistor and therefore this capacitance (Ciss) is compensated. (replace in similation LEDs with floating voltage source 5V)
Not. Because we kill not Miller but the Ciss. But your attachment very clearly shows that when using deep total negative feedback, Miller is practically absent.
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Yes, I understand what it does, I’m more surprised that he was able to get useful Vf at such low currents.
Thank you Marcel, while not directly relevant to the current discussion, it was still very interesting. I am learning a lot.
That's also covered, when you connect the nullator between drain and source (which is exactly what you do with your cascode, when you see each cascode transistor as an approximation to a nullator-norator pair).
Speaking of LEDs, I couldn't help myself and decided to run a simple (and very much flawed) experiment with a 12V PSU, a couple of LEDs and four resistors.
My verdict: real LEDs are much more useful at very low currents than their SPICE models.
Surprisingly, the red LED was still giving a decent amount of light at ~100uA of current (enough to be easily visible in a brightly lit room). The green LED I used was also glowing but very dimly, I had to cup it with my hand to see that it is on.
My verdict: real LEDs are much more useful at very low currents than their SPICE models.
Surprisingly, the red LED was still giving a decent amount of light at ~100uA of current (enough to be easily visible in a brightly lit room). The green LED I used was also glowing but very dimly, I had to cup it with my hand to see that it is on.
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There is something very, very fishy going on with LED models in LTspice.
Take this circuit for example:
It shows that the current through R2 is equal to ~390uA, which (according to my real-world measurements) should be enough to develop ~7.5V across D3-D6, but the current through the LEDs is shown as some minuscule value (2.9E-13) and the voltage drop across all four LEDs is just 1.2V.
For comparison, this is the circuit that @Nick Sukhov shows in his video (and which is supposed to be a working and tested circuit). I am showing only the relevant bits here:
Unsurprisingly, its DC operating points are also completely off in LTspice.
Take this circuit for example:
It shows that the current through R2 is equal to ~390uA, which (according to my real-world measurements) should be enough to develop ~7.5V across D3-D6, but the current through the LEDs is shown as some minuscule value (2.9E-13) and the voltage drop across all four LEDs is just 1.2V.
For comparison, this is the circuit that @Nick Sukhov shows in his video (and which is supposed to be a working and tested circuit). I am showing only the relevant bits here:
Unsurprisingly, its DC operating points are also completely off in LTspice.
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Thank you very much, sk. 👍
So what I need to do is connect the bottom of R18 in my circuit - see here:
... to the jfet Sources, instead of to ground (like I have it currently)?
C3 matters more than R18. You should get some capacitance reduction (about 8 pF) with C3 connected to the sources.
Aah, OK - thanks, Marcel. 👍
But only ~8pF! 😱
sk earlier said that there's probably about 60pF in Ciss from the 2SK70s ... how can I get rid of this?
Rough estimates:
Based on the curves in the Toshiba datasheet, I estimate that each JFET is biased at about 2 mA of drain current and has a transconductance of about 20 mS. Pretending that R4 is 50 ohm because it makes the calculation easier, the source AC voltage is then about 2/3 of the input AC voltage. Hence, the AC gate-source voltage is about 1/3 of the input signal voltage.
The Toshiba datasheet specifies a Crss of 6 pF at 10 V and a Ciss of 30 pF at 10 V. That means that the two JFETs together have about 48 pF from gate to source and about 12 pF from gate to drain.
Thanks to the series feedback, there is only 1/3 of the input AC voltage across the gate-source capacitances, so you see only 1/3 of 48 pF is 16 pF equivalent at the input due to the gate-source capacitances.
Assuming as a rough estimate that your cascode is ideal (that is, that Q1 has nullor behaviour), the drain AC voltage is either 0 or 2/3 of the input AC voltage, depending on how you connect C3. You therefore either get the full input AC voltage across the gate-drain capacitances or only 1/3 of it. The contribution to the input capacitance of the gate-drain capacitances is then either the full 12 pF or only 4 pF.
Total: either 28 pF or 20 pF.
Based on the curves in the Toshiba datasheet, I estimate that each JFET is biased at about 2 mA of drain current and has a transconductance of about 20 mS. Pretending that R4 is 50 ohm because it makes the calculation easier, the source AC voltage is then about 2/3 of the input AC voltage. Hence, the AC gate-source voltage is about 1/3 of the input signal voltage.
The Toshiba datasheet specifies a Crss of 6 pF at 10 V and a Ciss of 30 pF at 10 V. That means that the two JFETs together have about 48 pF from gate to source and about 12 pF from gate to drain.
Thanks to the series feedback, there is only 1/3 of the input AC voltage across the gate-source capacitances, so you see only 1/3 of 48 pF is 16 pF equivalent at the input due to the gate-source capacitances.
Assuming as a rough estimate that your cascode is ideal (that is, that Q1 has nullor behaviour), the drain AC voltage is either 0 or 2/3 of the input AC voltage, depending on how you connect C3. You therefore either get the full input AC voltage across the gate-drain capacitances or only 1/3 of it. The contribution to the input capacitance of the gate-drain capacitances is then either the full 12 pF or only 4 pF.
Total: either 28 pF or 20 pF.
Thank you for your detailed analysis, Marcel.
So it would seem that changing the way I connect them ... is not really going to affect the resulting capacitance load on the cart much?
BTW, if by "each JFET is biased at about 2 mA of drain current", you mean the current which is flowing through each jfet, from Drain to Source - I have this at about 4.8ma (75% of Idss).
If you are concerned about the input capacitance of the FETs and its voltage dependence, there is no need to parallel a K170 with a large gm (which also has a large input capacitance).
In the case of MM carts, the noise generated by the resistance of the cart itself and the noise generated by the load resistance (R15) of the cart due to the parallel resonance of the inductance and input capacitance becomes dominant at frequencies above 1kHz, and overwhelms the noise generated by the K170. Therefore, there is almost no S/N benefit from paralleling the K170.
@stratokaster83
Is it correct that the output is taken from the emitters of the cascode transistors (Q1, Q3)? Is it not a collector?
That makes a lot of sense. 👍
However, according to my LTspice simulations ... using 2 jfets in parallel increases the gain - which is helpful. (4 jfets in parallel ... even more so!)
Of course it’s not correct, a massive brain fart on my part. Thank you for noticing. 👍
Oh, yes, it was.
The right-hand circuit following this circuit is not depicted, but it is probably a passive EQ network.
The reduction in gain can be solved by increasing the load resistor (R1), but then the bias point and passive EQ network would also have to be reviewed. That would be troublesome.
Correct. 👍
Again, correct - but gain cannot be increased indefinitely, by raising the value of R1.
In my real-world measurements (ie. not LTspice simulations) ... there comes a point when an increased value of R1 doesn't deliver a corresponding increase in gain.
Hence the use of 2 jfets in parallel.
My comments in this thread are concerned with the posts on removing Ciss capacitance, so as to take away all cap-loading on the MM cart. But so far all I have been able to conclude is ... attaching C3 to the jfet Sources - instead of Ground - will get me part of the way there. 🙁
Maybe one more brain fart.
The approximate tail current of this circuit is 8 mA.
The voltage drop across the load resistors (R3 and R4) is therefore 15.6 V. The supply voltage is ±17 V, so the collector voltage both cascode transistors are low and must be in the saturation region.
This may be because the base of the cascode transistors are taking away the current that should originally flow to the LED due to the drop in hfe.
Try increasing R12 to reduce the tail current or lowering the load resistors (R3 and R4).