2 Pole (IP+VA) Stage

[U130421]

Lessons learned from preceding designed, I understood that it is unrealistic to seek distortions bellow 0.0001% at 10khz 30Vp, where noise dominates the measurements.
Instead of designing the IPS and VAS separately , Why not design them together . As my OS has a distortion 0.0013% for 30Vp 10khz , with hybrid version it showed that 30db NFB is sufficient. To have an overall gain of 25db, only 55db is necessary for the (IP+Va) stage to provide.
The circuit bellow has a distortion of 0.0005% , with mosfet inputs zvp3310 it is slightly lower, Jfets also can be tried out.

Hayk

 

[OldDIY]

In the diagram, the inductance L1 is connected to the ground, and not to the plus?
Is it a correction element or a cascade load?

 

[U130421]

It is correct. Instead of using a CCS + servo to bring the output to 0 volt, an iductance can replace both. Of course the CCS saturates but not the unloaded inductor. The negative excursion can reach 36V without increase in distortion.

 

[U130421]

I am greatly deceived by the 2 pole performance. Very slow slew rate , unavoidable overshoot. See the comparison, both are 20khz cut, 30db NFB.

The 2 pole.

The 1 pole.

Hayk