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https://forum.vegalab.ru/showthread.php?t=87194
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https://forum-vegalab-ru.translate...._sl=ru&_x_tr_tl=en&_x_tr_hl=ru&_x_tr_pto=wapp
Yes it will work.
But too much output voltage headroom will be unused due to low transconductance of laterals.
They need at gates up to 8 volts more than source. this can be achieved at one power rails without bootstrapping.
But U1 should not be used with a passive voltage source.
Just simulate CMRR and you will see how Early effect provides pfssthrough for common mode noise to a differential output error.
Try to use active or cascoded current source in input stages.
I have worked and tried for lower THD.
I could get it downto 0.0005%.
But when I now added compensation with C1, THD is 0.0006%.
I will not work any further on this amplifier.
Here is the endresult:
I could get it downto 0.0005%.
But when I now added compensation with C1, THD is 0.0006%.
I will not work any further on this amplifier.
Here is the endresult:
Sad.
1. Active or cascoded CCS, greatly improves CMRR and noninverting THD.
2. Input LTP degeneration drops gain but increases acceptable input swing.
3. There must be CCS'es, this will greatly improves looopgain and THD figures.
4. Main VAS must be cascoded to eliminate Early effect. Idle shoulder are better to have tracking active shoulder voltage.
5. Since negative tempco over ~200 mA idle current just a simple LED can greatly improve gate charge flow.
6. Too much load capacitance, VAS strangled. No stabilizing resistance, so PCB leaks will be unpredictable influences on loopgain. It's better to add driver stage which allow to reduce capacitance at least 20x times.
7. Too much gate resistance, such a laterals already have polysilicon gates which increases resistance from ones MHz so they're easy load to drive with modern BJTs.
Uffff. Too much work, sad but true.
