What is unique is the use of folded cascode.
Simulation shows THD 0.00032% but what the real value is we can not know.
Let us say the distortion should be low.
Folded cascode makes the input pair drive the output.
Because EXICON Laterals are easy to drive, it works.
Simulation shows THD 0.00032% but what the real value is we can not know.
Let us say the distortion should be low.
Folded cascode makes the input pair drive the output.
Because EXICON Laterals are easy to drive, it works.
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I thank you @Nelson Pass for the LIKE.
At last somebody that can see the good in my circuit.
Better like I could not get.
Let us see if there are a few more that are interested 🙂
At last somebody that can see the good in my circuit.
Better like I could not get.
Let us see if there are a few more that are interested 🙂
Whenever I see the current mirror looping around VAS, it usually a good candidate to convert it into fully symmetrical complementary circuits without adding too much complexity. In this design, you could add another differential input pair with npn transistors so that you don’t need to use the current mirror.
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Like this, I changed compensation a little bit.
Edit:
Like this, I changed compensation a little bit.
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I have seen that in a lot of my tries with Mosfet output.
The speed is so good to a few volts out but the VAS current is not enough for a slew rate giving full output at such frequencies.
I guess this amp will maybe make more than 100 kHz full power with low distortion and that is good enough for most of us.
The speed is so good to a few volts out but the VAS current is not enough for a slew rate giving full output at such frequencies.
I guess this amp will maybe make more than 100 kHz full power with low distortion and that is good enough for most of us.
I think the model I use is more aligned with the datasheet, but with high THD.
Looked at this thing. The gm is evenly spaced out when Vgs >2V.
Vgs from 1V to 2V is about half the gm that is above 2 Vgs. Thus, you should find an optimal bias point around 1Vgs. My model exhibits the same behavior. Over that point, the THD degrades with the bias increasing.
Looked at this thing. The gm is evenly spaced out when Vgs >2V.
Vgs from 1V to 2V is about half the gm that is above 2 Vgs. Thus, you should find an optimal bias point around 1Vgs. My model exhibits the same behavior. Over that point, the THD degrades with the bias increasing.
I would put a 1000uF in parallell with the led to prevent a max DC out at startup.
Do you know how the distortion figure will look like?
Do you know how the distortion figure will look like?
Simple folded cascode does not need much compensation.
I have worked on a clone of AD8021 simplified:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad8021.pdf
I have worked on a clone of AD8021 simplified:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad8021.pdf
About .001% for me and .004% at higher power.
Without very specific operating points yes noticed it fails to .01%
Depending on the vas current and loading from the bias setting resistor
for the output section.
seems almost 9ma of current? for the differential.
Seems pretty fun for the simplicity, a more complicated output section
might keep it more consistent.