USB processor clock has impact on audio, tested on four different usb boards.
It is only 1.5-3 USD to try, perhaps later some members will confirm my experience. Huge improvement I've recieved on SA9227 usb receiver with independent 45/49 clocks with ES9039q2m in ASYNC mode without MCLK, with swapping 12Mhz processor crystal to cheap normal oscillator. Near the same was on another XMOS boards. This thing don't need and perhaps can't to be measured, it need to listen.
It is only 1.5-3 USD to try, perhaps later some members will confirm my experience. Huge improvement I've recieved on SA9227 usb receiver with independent 45/49 clocks with ES9039q2m in ASYNC mode without MCLK, with swapping 12Mhz processor crystal to cheap normal oscillator. Near the same was on another XMOS boards. This thing don't need and perhaps can't to be measured, it need to listen.
Sorry, but USB clock has no impact on audio when UAC2 interface is bit perfect to 32 bits. If it isn't bit perfect then there is something seriously wrong and swapping clock is not likely to help. Claims from listening when no proper controls are used and AB is not even possible are as convincing as fairy tales.
If the USB clock is causing some real audible effect, then it would almost certainly be due to analog noise side-effects and not because of bit errors. A well-designed isolator/reclocker system would hopefully take care of any poorly defined analog USB subsystem noise problems more effectively than a poorly defined reduction in USB clock jitter related noise.
This was about USB clock jitter, not USB clock noise (actually that 26MHz crystal is a reference clock, not USB clock). How would jitter in this reference clock cause audible analog noise side-effects (whatever that means)?
Don't know offhand. I would have to see one change the sound before I would start chasing around trying to figure how it was doing it.
the problem should be that too many ESS chips are using its own local clock but not the MCLK supplied by usb board? as only MCLK should matter in any conventional architecture..
That's true to a first approximation, at least. IOW, it is a model of a physical system's intended behavior. Maybe the actual physical system is a little bit more complex than the model being used?
Reason I have some doubts about the simple model is because once I did an experiment with an ESS dac where I moved I2S signals in 200ps steps relative to MCLK. IMHO there was a very slight sweet spot at one timing step, but it was really slight. I had to test myself many times before deciding it was real. I later did a similar experiment with AK4499EQ where MCLK series damping resistance was adjusted to affect MCLK timing relative to I2S bus timing. A friend could hear an exact spot to within 5-ohms of damping resistance where he said there was a peak in soundstage depth information. I couldn't hear it myself at the time, so I tried to fool him multiple times by making him find the spot again. I didn't know if it was the same spot or not while we were doing the listening test. Only after he said it was the right spot and we stopped was when I measured the adjustment pot resistance. Each time it came to within the same 5-ohm spot. Total resistance was well over the theoretical 33-ohms most commonly used. It was closer to 100R or slightly more. Anyway, yeah, these were not strictly controlled DBT, but it was enough casual evidence to make me wonder if the system model of nothing but MCLK alone being able to effect sound might not be a little bit oversimplified.
Of course, the above is a very different question than the one we started with. It had to do with a non-audio clock in the USB board circuitry. That's something I never thought worth looking at, but who knows maybe there could be some unexpected side-effect. I'm still not going to bother with looking at it so long as I am doing what I feel is reasonably good reclocking.
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