Folks,
Over in the TDA1541 Meta Thread we had a lot of input to analyse the TDA1541, what makes it tick and how.
https://www.diyaudio.com/community/threads/building-the-ultimate-nos-dac-using-tda1541a.79452/
What I would like to do here is extract the practical part and propose a complete DAC design that may be realised as open source group project.
I would first propose a basic structure.
There will be a main board for the TDA1541 with a super capacitor based "stacked" 20V supply, optimised layout for the various decoupling capacitors needed as discussed in the other thread.
There will be attenuator/slew rate limiter circuits and a set of Flip-Flip's for reclocking and / or division of BCK & LE/WCK as well as a DEM Clock divider from a 512X MCK. The aim is to run a continuous BCK with the lowest frequency possible, so the default option will be I2S with 32X FS BCK, as the lowest sensible without FPGA/CPLD/MCU etc.
There will be embedded clock generation with 22.5792 & 24.576MHz clocks and dividers that allow full slave operation of a frontend at either 32X FS or 16X FS. It will also accept two external 512X MCK from (for example) an SPDIF receiver or USB Board with embedded MCK out that cannot be slave clocked from our on board clocks. Super capacitor based 5V supply.
Space for an analogue stage "plug in" to keep the choice open. My own intention is to use a SuperSziklai Pair based design detailed in the original thread.
Space for a SAA7220 socket that could be filled with an SAA7220 or any PCB holding any FPGA, CPLD, ASRC or whatever. Space will be be left around for a larger PCB to fit this socket. Again, this leaves the choice what goes into this socket (including nothing) to the builder. For my own setup an SRC4190/AD1896 will be fitted to operate as 64X FS to 32X FS I2C converter and as optional dejiiterer for jittery SPDIF Receivers and sources that otherwise sound worse than ASRC engaged.
Anything else will go. Pick your poison. If the 74ACT2226/28 returns from "active but zero stock deads" it may become the FIFO based I2S 2 SIM converter discussed here, otherwise SRC4190 in bypass makes a swell FIFO & format converter with a bonus ASRC):
https://www.diyaudio.com/community/...g-discrete-logic-collaborators-wanted.424459/
Input choices will include standard (Amanero) footprint for USB Boards (mostly XMOS) with isolation via SPDIF (no I2S digital isolators allowed, why will be discussed in good time) and a clock feedback from our crystal clocks with 44.1/48 base selection via opt-isolated pin, probably at least two selectable options.
SPDIF Inputs with SE BNC, XLR AES and Optical plus USB. The SPDIF Receiver position gets a CS8412 DIP socket that accommodate any number of SPDIF RX Solutions, all the way to "roll your own" with FPGA/CPLD/CPU.
I'd draw a block diagram if needed... is it?
So, if anyone is interested in making this a reality as an open source project, join into the discussion.
This is not a channel to debate fundamentals, redebate stuff from other threads or "can you make it into this thing?". If you choose to actively contribute time, effort or money to the project you can of raise suggestions.
I expect to hear crickets, cicadas and the occasional lizard chitering on this thread, but G*d love's a trier.
Thor
PS. As an additional note, all real PCB work will be in Altium, not Kicad or similar educational toys. All simulations and initial schematics capture in TINA-TI. This is non-negotiable.
If you need help with Altium Designer, we can talk in private how to use the free download with full functionality for evaluation and educational purposes beyond the eval time limit. TINA-TI, download at TI.
Over in the TDA1541 Meta Thread we had a lot of input to analyse the TDA1541, what makes it tick and how.
https://www.diyaudio.com/community/threads/building-the-ultimate-nos-dac-using-tda1541a.79452/
What I would like to do here is extract the practical part and propose a complete DAC design that may be realised as open source group project.
I would first propose a basic structure.
There will be a main board for the TDA1541 with a super capacitor based "stacked" 20V supply, optimised layout for the various decoupling capacitors needed as discussed in the other thread.
There will be attenuator/slew rate limiter circuits and a set of Flip-Flip's for reclocking and / or division of BCK & LE/WCK as well as a DEM Clock divider from a 512X MCK. The aim is to run a continuous BCK with the lowest frequency possible, so the default option will be I2S with 32X FS BCK, as the lowest sensible without FPGA/CPLD/MCU etc.
There will be embedded clock generation with 22.5792 & 24.576MHz clocks and dividers that allow full slave operation of a frontend at either 32X FS or 16X FS. It will also accept two external 512X MCK from (for example) an SPDIF receiver or USB Board with embedded MCK out that cannot be slave clocked from our on board clocks. Super capacitor based 5V supply.
Space for an analogue stage "plug in" to keep the choice open. My own intention is to use a SuperSziklai Pair based design detailed in the original thread.
Space for a SAA7220 socket that could be filled with an SAA7220 or any PCB holding any FPGA, CPLD, ASRC or whatever. Space will be be left around for a larger PCB to fit this socket. Again, this leaves the choice what goes into this socket (including nothing) to the builder. For my own setup an SRC4190/AD1896 will be fitted to operate as 64X FS to 32X FS I2C converter and as optional dejiiterer for jittery SPDIF Receivers and sources that otherwise sound worse than ASRC engaged.
Anything else will go. Pick your poison. If the 74ACT2226/28 returns from "active but zero stock deads" it may become the FIFO based I2S 2 SIM converter discussed here, otherwise SRC4190 in bypass makes a swell FIFO & format converter with a bonus ASRC):
https://www.diyaudio.com/community/...g-discrete-logic-collaborators-wanted.424459/
Input choices will include standard (Amanero) footprint for USB Boards (mostly XMOS) with isolation via SPDIF (no I2S digital isolators allowed, why will be discussed in good time) and a clock feedback from our crystal clocks with 44.1/48 base selection via opt-isolated pin, probably at least two selectable options.
SPDIF Inputs with SE BNC, XLR AES and Optical plus USB. The SPDIF Receiver position gets a CS8412 DIP socket that accommodate any number of SPDIF RX Solutions, all the way to "roll your own" with FPGA/CPLD/CPU.
I'd draw a block diagram if needed... is it?
So, if anyone is interested in making this a reality as an open source project, join into the discussion.
This is not a channel to debate fundamentals, redebate stuff from other threads or "can you make it into this thing?". If you choose to actively contribute time, effort or money to the project you can of raise suggestions.
I expect to hear crickets, cicadas and the occasional lizard chitering on this thread, but G*d love's a trier.
Thor
PS. As an additional note, all real PCB work will be in Altium, not Kicad or similar educational toys. All simulations and initial schematics capture in TINA-TI. This is non-negotiable.
If you need help with Altium Designer, we can talk in private how to use the free download with full functionality for evaluation and educational purposes beyond the eval time limit. TINA-TI, download at TI.
Seems quite flexible both for filter and receiver. I'm in favor for jlsound's i2soverusb so I'll wait for the explanation why not include an i2s isolator.
I'm guessing that the super capacitor will be on a separate pcb beneath the DAC pcb and someone could use his own psu instead.
I'm guessing that the super capacitor will be on a separate pcb beneath the DAC pcb and someone could use his own psu instead.
That's the point.
Whatever.
In short, massive amounts of jitter, power supply noise and radiated noise. I used them in some products. If there is any way to do without the, I will do without. These things are fine for isolating other stuff. Audio - less so.
Not my intention. That would make no sense and severely compromise the Supercapacitors.
Thor
Okay. But some people have significant problems with conducted USB bus ground/power EMI/RFI noise from PCs affecting dac sound. Designing around the problems introduced by isolators (and problems persisting because of their limitations) may add cost and complexity most users aren't willing to pay extra for. However, for a top tier dac I would vote for some insurance against ground loops involving the AC line, PCs, and downstream devices following the dac. May not show up very well in standard measurements, but there is such a thing as "veiled" sound. Maybe less of a problem with TDA1541?
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Why are you waiting for collaborators? You might as well wait for Godot. You know what you are doing and you know what you want to do. Just do it and put it out there. It will be built those who are interested and for those who are not there are cheap chinese dacs and $2000 clocks.
How much for a properly working TDA1541A with two original gold crowns (or better)? Maybe $800? More?
This means exclusion of many possible collaborators (possibly also the Mac using ones that use KiCAD as it runs natively on their Macs). It seems you don't need or really want them either.
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...also what's the life time to be expected from those chips? It seems they are getting a bit old from now: my experince is they start to fail here and there in CD players etc., and most people would take them out from cheap donor players - so I wonder how much of a future the TDA1541(a) actually has...
One can still collaborate and not use altium. Pcb design isn't all about the tool used (very least so). To me, altium is very well worth learning, and is a more powerful tool (and it shouldn't be compared, not the same class of tool). But one can contribute with layout ideas, experience and recommendation.
Please keep on topic subject.
Please keep on topic subject.
Sure. I did not state "no isolation", just no digital signal isolators based on modulated RF.
Well, this is an interesting topic. But I prefer simpler workarounds.
Oh, absolutely, all inputs need to be isolated. Just not with any of these isolator chips everyone insists on using without thinking and testing, cause "solated mo betta, innit?
You are talking about conducted interference, it actually is unrelated to Dac chips or analogue circuitry inside the DAC (or digital in fact).
I am not. I am offering the opportunity.
If I do it myself, invest my time only it will not be open source. I'm not a charity.
Thor
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Well, it is what I use and for good reasons. I for one will not use KiCAD if I have better alternatives. It's just not very good.
If I do not draw PCB's, I guess it doesn't matter, but I suspect I will.
Thor
Mode conversion of longitudinal noise is not unknown. Also, sometimes noise is differential between USB ground and its +5v. I've seen both propagation modes cause problems.
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My time in with this project is with pcb design, as i'm lacking in digital circuit domain and can't contribute much there. Analog will be end users choice, but i'll be making several for this as well so one can choose. Baxandall cc is already trialed and tested, sounding good and working proper.
Longitudinal noise is a antique notation for common mode noise.
And yes, it is not unknown, but a strong indication of p!ssp0rr design.
While Galvanick Insulation can solve the problem, if done in stupid ways it creates more problems than it solves.
The key element in problem solving is to recognise the problem correctly.
Conducted EMI is common mode CURRENT in the ground and/or other conductors of our incoming cable.
For USB noise on the Data wires is generally cancelled by the differential nature of USB. USB has substantial tolerance to common mode noise build in.
So we are dealing with noise via GND and VBUS. VBUS is kept at GND level on the Upstream port, soon the downstream port we place a sufficiently large value low ESR, low ESL capacitor to sink noise in the band of interest into the USB Ground. As only a Mike Oskar Romeo Oskar November would power any USB Audio device from Bus Power that's almost it, we only need to make sure to have a few mA load on VBUS.
We now have a differential USB signal that can handle a minimum of 100mV Peak common mode noise and a noisy ground with between 0.1 to 5mA RMS current (mainly mains frequency and harmonics) flowing. This current originates as mains noise referred to Earth (both literally and in the sense of the PEN connector of the mains system.
Our challenge is to allow this current to circulate without it leading to a conversion of common mode current noise into differential voltage noise first for our circuit and second for associated equipment. There is an electrical circuit challenge here and a PCB layout challenge.
If both are addressed, there is no pressing need for "Galvanick Insulation", especially not for chip's with so much jitter that it can be seen on the scope with a naked eye and radiated (as well as power supply) noise in the 100's of MHz range that an antennae picks up from a meter away.
The solution is basic "sound" (pun intended) electric design, not "Jitters'R'Us" canned isolator IC's. In fact, isolation may not be needed or useful.
Thor
PS, USB isolators also sux, fairly high levels corrupt data frames on isochronous High Speed USB transfers. Brrrhhhhh.....
Nowadays dacs are DS where only MCK is critical. In proper design MCK is on the clean side so isolation of other signals does not impact MCK. For those obsessed with using obsolete DAC chips which rely on BCK or LRCK reclocking with clean MCK is possible.
Is that really so? Not my experience, BWTFDIK.
That is an idealised claim not born out in the real world.
Again, it is hard to completely get rid of accumulated switching noise form too many complex IC's in CMOS tech. But who am I to tell you what you should do? And I don't tell you. Please keep doing what you are doing. Nothing of what you do is in the least interesting or relevant in context.
I do greatly appreciate your timely, witty and well meaning contributions, but you are wasting your time. I guess you, like pretty much everyone else who posted so far failed to read the terms of reference in the first post in the thread.
Thor
If you spout your opinions as universal truths you should expect others to voice their point of view as well. If you don't want any dissonance you should create a member blog instead.
It is just because of the way how any digital circuit in ASIC is designed. Any external signal is synchronized into the digital circuit clock domain before any processing. And any modern DAC has digital front end.
Opinions? Experiences... Actually. I did not claim universal truth, ALL my statements are qualified.
In fact, the one in this conversation who makes absolute and universal and unqualified (pun and double entendre intended) statements happens to be you.
So: "If you spout your opinions as universal truths you should expect others to voice their point of view as well.".
But I will not come to your threads to expose your ignorance. Life's too short and all that. Blocked. Have a good life.
But does that reliably mean only MCK matters, not noise on power ground pin's, general system noise etc. et all? Interesting.
Thor
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I was talking about BCK, WCK, DATA and MCK signals only. Among then only clean MCK is really important.