Could you please read the spec? It is perfectly I2S compliant to change data and word select after a rising edge, as long as the hold time is at least 0 ns.
That's in direct contradiction with the I2S specification. It is perfectly acceptable (and very usual) to change the word select around the falling edge, but it is also acceptable to do it at or just after the rising edge. Just before the rising edge is not, as that would violate the set-up time requirement.
Anyway, the specs are in the links of post #19, anyone can read them for themselves.
From the 4490 datasheet - Note 21. BICK rising edge must not occur at the same time as LRCK edge.
I know, that's precisely why the 4490 is not I2S compliant. It should support 0 ns hold time, so note 21 already shows it is not compliant. The tables and timing diagrams show they miss the spec by 5 ns.
Anyway, this discussion is both off topic and not going anywhere.
Anyway, this discussion is both off topic and not going anywhere.
[6] The data set-up and hold time must not be less than the specified receiver set-up and hold time.
More useful is to read AKM datasheet before designing the reclocker if you expect it to work with AKM dacs.
Sure, if you only want it to work with that specific AKM DAC.
The whole purpose of the I2S standard is to ensure interoperability, so you could design a reclocker or audio streamer or whatever that works with any I2S DAC without having to read the datasheets of all of them, including the ones that don't exist yet. That's completely undermined when companies start cheating, like AKM does.
The whole purpose of the I2S standard is to ensure interoperability, so you could design a reclocker or audio streamer or whatever that works with any I2S DAC without having to read the datasheets of all of them, including the ones that don't exist yet. That's completely undermined when companies start cheating, like AKM does.
...which specified receiver hold time should be 0 ns or less according to the table above that note (receiver lower limit for the hold time max. 0 ns).
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As I said there is rarely any need for reclocking of I2S signals with modern DS dacs.
You may also ponder why universal USB-I2S board (JLSounds I2SoverUSB) uses a Xilinx CPLD for reclocking instead of a much simpler flip-flop scheme.
Early reports using the reclocker for Marcel's RTZ dac is that its well worth the effort.
JLSounds I2SoverUSB never sounded so good.
Its also easy to add very low jitter delays after a relocker, if desired. (I could have built some into the reclocker board, to be selected with solder jumpers.)
Isolation may sometimes be of benefit as well.
As always, it depends.
JLSounds I2SoverUSB never sounded so good.
Its also easy to add very low jitter delays after a relocker, if desired. (I could have built some into the reclocker board, to be selected with solder jumpers.)
Isolation may sometimes be of benefit as well.
As always, it depends.