Do Multiplexer ICs and CPLDs cause jitter?

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uLdac

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Joined 2023
#1
Any experienced digital experts here?

Someone in some threads said that Multiplexer ICs and CPLDs can cause jitter, so you should put a reclock behind them.
I'm sure experienced engineers know this well.
Is this actually true for 74lv157 or CPLD?

If the jitter for each line is not random, but the same, and short enough,
I think it can be adjusted with series resistors. What do you think?

Of course, jitter will have different effects on different DACs, and in a DAC like the AKM that is jitter tolerant, it may be audibly or measurably meaningless.
 
#2
Just about anything you put in the clock path will cause jitter to some extent. A part of it is random jitter due to ordinary circuit noise in the multiplexer or CPLD, but you can also get jitter due to supply ripple modulating the delay of the multiplexer or CPLD, or due to mixing products with other signals that the multiplexer or CPLD is processing.

Whether the jitter is bad enough to worry about is impossible to answer without further information about your set-up and requirements.
 
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#4
For a simple selector, a small relay with gold contacts may be the best choice. That is if you want to know how much some jitter might matter. Then an analog switch could be compared to the relay. Then maybe an analog switch with, say, noisy Vdd could be compared to a relay, and so on. All it sometimes takes to cause some audible problem in an otherwise pristine system is having something like, say, maybe a noisy trace or noisy ground currents running under a sensitive analog device (such as a clock oscillator). Little mistakes like that can add up enough so that fixing just one of them may not be very noticeable.
 
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#5
Modern DS dacs (e.g. AKM and ESS) need jitter-free MCK. On those dacs reclocking of I2S signals (SCK, WS, SD or BCK, LRCK, SD) is not necessary if MCK is clean.
Actually reclocking of I2S signals with modern DS dacs can be detrimental as there needs to be a separation between BCK and LRCK edges to avoid violation of setup and hold times. E.g. AKM dacs require min. 5 ns between BCK and LRCK edges.
 
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#7
uLdac said:
@MarcelvdG
That's a clear answer. Do noise and ripple mean power noise and coupled EMI? It would be a good idea to study the internal structure and principles. For a simple selector, an analog switch IC might be good. thank you
Click to expand...

The noise I meant is ordinary circuit noise: thermal noise in MOSFET channels, 1/f-noise due to all sorts of obscure effects at the semiconductor surface or in the gate oxide, that sort of thing.

The ripple refers to the supply and ground voltages varying over time. That can be due to coupled interference.

When your CPLD (or multiplexer) processes other signals than just the selected clock, it will disturb its own supply and ground. The switching current spikes due to those other signals will cause voltage drops across the supply and ground wire inductances that will interfer with the processing of the desired clock.
 
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#8
Last I checked, the I2S signals were re-clocked by an internal PLL in the ESS parts. I bet that's the case for the AKM as well. The PLL acts like a lowpass filter on the incoming clock, so as long as the incoming clock jitter isn't outrageous (> 50 ps if memory serves) it'll have no impact on the internal clock jitter in the DAC. The jitter internally in the DAC should be dominated by the jitter of the VCO in that PLL clock jitter cleaner.

Tom
 
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#9
I did that experiment with ES9038Q2M. Not only was the jitter of the internal ESS ASRC DPLL audible and objectionable, but there was also a sweet spot in the MCLK timing relative to the other I2S signals. MCLK was adjusted in 200ps increments and there was one increment which was very slightly less distorted/noisy.

If other people don't hear that stuff then they don't hear it and we will disagree. Okay with me, we don't always have to agree.
 
#12
All this stuff is good in response to the OP's question. However, has the OP really asked the right question or questions?

Maybe it would be better to say, "this is what I want to do..." And, "this is how I am thinking of doing it..."

"Am I asking all the right questions?"

Including, "is there a simple fix in case the reclocking scheme fails?" Or, "should I read the datasheet first to see the timing requirements?"


Just saying, obviously jitter is only one concern. Taken out of context of other possible concerns, is a limited focus on jitter alone likely to lead to an especially good design?
 
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#19
#20
It stands to reason that you cannot have a rising edge of bitclock coincident with a change of WS. Data is valid on the rising edge of bit clock. In a correctly functioning setup any change of WS will be coincident with a falling edge of bitclock.

I2S_4490.gif
 
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