Return-to-zero shift register FIRDAC

If you reduce C15, C26, C42 and C53 on the DAC main board to 4.7 nF and then add 1.8 mH inductors and 15 nF capacitors, you have approximately third-order Butterworth filters at 45 kHz. You may need to add coupling capacitors if you want to get rid of the 1.25 V DC level.
Thanks Marcel. I've ordered the revised caps so I will build one of my RTZ DAC boards as standard to use with your op-amp based filter board and the second to explore alternative output filter arrangements.
 
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Hello,
Here is the schematic of the board i am trying to build, the idea is a IO board under the dac. I would greatly appreciate feedback, as i said it's my first schematic and pcb. A friend will help me for the routing, there is too much subtlety for me.
It's based on the PPY's Reclocker for the bealgebone. I inserted the FPGA modulator between the BBB and isolators. Silent Switcher with 5.5v => ldovr lt3045 5v for the isolated side, and a DC-DC isolated block for the fpga and BBB.
I will also add a lipo battery for the BBB.
 

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Last edited:
Hello,
Here is the schematic of the board i am trying to build, the idea is a IO board under the dac. I would greatly appreciate feedback, as i said it's my first schematic and pcb. A friend will help me for the routing, there is too much subtlety for me.
It's based on the PPY's Reclocker for the bealgebone. I inserted the FPGA modulator between the BBB and isolators. Silent Switcher with 5.5v => ldovr lt3045 5v for the isolated side, and a DC-DC isolated block for the fpga and BBB.
I will also add a lipo battery for the BBB.

I have two comments and a question:

1. Several different wires have the same label, for example MUTE. If these are just comments, there is no problem, but if these are wire labels (which define node names), all wires with the same name are shorted. You can fix that by using MUTE_xxx instead, where xxx is to be replaced with a postfix that is unique for each wire.

2. If you want to keep the clock as clean as possible, with as little data-to-clock crosstalk as possible, use the U.FL bit clock input of the DAC board rather than the bit clock pin on the Amanero-style header. If you do use the header, make the connection as short as possible: just two headers, no flatcables. This poses mechanical constraints: it has to fit. You could, of course, design the board for both options, using 0 ohm resistors to only connect what you use.

3. What is the purpose of U6? Are two different pin-outs used with Beagle Bones?
 
I have two comments and a question:

1. Several different wires have the same label, for example MUTE. If these are just comments, there is no problem, but if these are wire labels (which define node names), all wires with the same name are shorted. You can fix that by using MUTE_xxx instead, where xxx is to be replaced with a postfix that is unique for each wire.

2. If you want to keep the clock as clean as possible, with as little data-to-clock crosstalk as possible, use the U.FL bit clock input of the DAC board rather than the bit clock pin on the Amanero-style header. If you do use the header, make the connection as short as possible: just two headers, no flatcables. This poses mechanical constraints: it has to fit. You could, of course, design the board for both options, using 0 ohm resistors to only connect what you use.

3. What is the purpose of U6? Are two different pin-outs used with Beagle Bones?
Hello,
Thank you for your answer.
1. Yes these are just comments to help me read the schematic.
2. I was planing to put all the clock circuitry very close to the Amanero connector. But i think i will listen to your advise and put some U.FL.
3. If i understand correctly, DSD2 and LRCLK should be on the same signal, but the BBB do it with two different GPIO. So you need a multiplexer to switch between the two, with DSD_On as the trigger.
 
A belated merry Christmas to everyone!

Received my PCBs today.

74FBB1FF-2AB8-45FE-8CCC-5E3631C0F7B4.jpeg
 
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