During the lockdown, I started designing a completely solid-state guitar/bass preamp centered around opamps for clean gain and diode clipping + JFET colouration for overdrive and distortion. It features pre-emphasis and subsequent de-emphasis in order to allow higher gain (as of now, the pre-emphasis is a +10 or +16dB high shelf, with the two "shelves" being approx. below 80Hz and over 1 kHz, and the de-emphasis is a corresponding and reversed bass shelf; this would also allow a +6dB bass boost or +6dB added brightness). I might rework the pre-emphasis and de-emphasis to allow bypassing it (and have essentially a flat response within the passband) and tweaking the values a bit (for example +6dB and +12dB). Also, I might add a HPF for guitar use (as it is now, the HPF is at around 30Hz).
The diode from gate to source on the first JFET is to avoid heavy gate conduction, and is there only for pathological conditions (extreme peaks), but I could use an appropriately chosen diode + zener diode to ground I suppose (or just not bother). The second JFET employs essentially a semi-forced source voltage, fixed by an opamp, and it behaves well in simulations. I have quite a few OPA2134 at home, but I think that some of the opamps would work well with an NE5532 in their place. The tone control is essentially a Big Muff tone control with selectable values (I have a 6-way switch, why not put it to use?). The attached PDF lacks the clipping indicators, power supply and regulation (which is dual +/-15V; as for regulation, I was thinking of just using a zener regulator for the opamps, as they have very high power supply noise rejection, and a regulator chip just for the JFETs, which could even run at a higher voltage if necessary), active EQ, vibrato and spring or digital reverb (I could use either).
The diode from gate to source on the first JFET is to avoid heavy gate conduction, and is there only for pathological conditions (extreme peaks), but I could use an appropriately chosen diode + zener diode to ground I suppose (or just not bother). The second JFET employs essentially a semi-forced source voltage, fixed by an opamp, and it behaves well in simulations. I have quite a few OPA2134 at home, but I think that some of the opamps would work well with an NE5532 in their place. The tone control is essentially a Big Muff tone control with selectable values (I have a 6-way switch, why not put it to use?). The attached PDF lacks the clipping indicators, power supply and regulation (which is dual +/-15V; as for regulation, I was thinking of just using a zener regulator for the opamps, as they have very high power supply noise rejection, and a regulator chip just for the JFETs, which could even run at a higher voltage if necessary), active EQ, vibrato and spring or digital reverb (I could use either).
Why? The gate is rated 10mA. With 2k+1k in front, you are never going to blow it up. The Gate is an excellent diode.
If you use Zeners for op amp regulation, run them with plenty of bias current.
Around 30% - 40% of their power rating is good. If that's not enough current,
use a higher wattage Zener.
Around 30% - 40% of their power rating is good. If that's not enough current,
use a higher wattage Zener.
Interesting project.. 😀 Been a long time since I thought about this sort of stuff.
Was wondering location of SW4 and RC networks was a mistake? (It won't do anything to the sound in the present location.) Also with the high input resistance and comparatively low value of the feedback resistor it seems like a low noise jfet opamp might be good choice here to get offset and input current noise down. Is C28 actually 100nF?
The U6A circuit is probably an oscillator at some settings. Seems like TP3 should go to the non inverting input of U6A, and TR5 could be eliminated and the whole configured for the maximum gain you think you might need. C25 and R26 seem to be in the wrong place. Consider sticking a small resistor in series with RV4B between it and the op-amp inverting input. What is the function of R23?
Was wondering location of SW4 and RC networks was a mistake? (It won't do anything to the sound in the present location.) Also with the high input resistance and comparatively low value of the feedback resistor it seems like a low noise jfet opamp might be good choice here to get offset and input current noise down. Is C28 actually 100nF?
The U6A circuit is probably an oscillator at some settings. Seems like TP3 should go to the non inverting input of U6A, and TR5 could be eliminated and the whole configured for the maximum gain you think you might need. C25 and R26 seem to be in the wrong place. Consider sticking a small resistor in series with RV4B between it and the op-amp inverting input. What is the function of R23?
Last edited:
I wanted to say..."If true re R26+C25 I see other goobers like it."
Also look at Sheet 4. Same thing.
Also look at Sheet 4. Same thing.
On page 2 the AC output of U2A (assuming a ±15V supply) will flip-over the direct-driven FET strung between +15V and GND.
That FET circuit has problems.
Are you going after asymmetrical clipping with the two different diode+LED stacks after U2A?
That FET circuit has problems.
Are you going after asymmetrical clipping with the two different diode+LED stacks after U2A?
As above, what is the function of 1K Rs at each 2134’s IN+?
With Boost Tone RV4A pins 2 & 3 connected a capacitor voltage divider is created from C17 and C21 plus the C=>Gnd load placed on Q2’s drain. Is that according to plan?
I don’t understand the two selections for loading Q2’s drain provided by the “Bass Boost” SW3. EG: In the 250K position = a ~1Hz HPF result and in the other position = a Q2 drain voltage reduction cornered at some frequency ((i.e. Q2’s resistive drain load(?)) against the 22K R22 and 33nF C30).
Yes U6A’s IN- does not like being hard grounded or hard connected to a low-impedance AC source, by TP3.
Correct me if I didn't see something here.
With Boost Tone RV4A pins 2 & 3 connected a capacitor voltage divider is created from C17 and C21 plus the C=>Gnd load placed on Q2’s drain. Is that according to plan?
I don’t understand the two selections for loading Q2’s drain provided by the “Bass Boost” SW3. EG: In the 250K position = a ~1Hz HPF result and in the other position = a Q2 drain voltage reduction cornered at some frequency ((i.e. Q2’s resistive drain load(?)) against the 22K R22 and 33nF C30).
Yes U6A’s IN- does not like being hard grounded or hard connected to a low-impedance AC source, by TP3.
Correct me if I didn't see something here.
You should never depend on a POT for a bias reference. There should be zero DC in gain controls and DC bias pot failure should result in reduced bias, not a runaway condition. I think another post mentioned ~U6A where a pot can leave an op-amp with both inputs grounded and therefore bad things will happen. There are other circuits that seem somewhat inefficient but that may be an artistic choice. When I made instrument gadgets, I spend a lot of time listening to it and tuning the sound by ear. Don't use "engineering" to make decisions about things like tone controls.
Given that Acrobat no longer rotates images for free, I should just remove it, but if you want to use a pdf, please make the images right side up.
Given that Acrobat no longer rotates images for free, I should just remove it, but if you want to use a pdf, please make the images right side up.
Where does a bias reference depend on a pot? Are you referring to the trimmers? With FETs, trimmers are a bit of a necessity. For the rest, it is true, in order to have the FET work correctly you actually need to reduce the input level in most cases, so there is some inefficiency there. I could use the first opamp as a simple buffer with no gain, but then I would attenuate a low level, introducing noise. I'd rather attenuate a higher level.
If an op-amp input is open, it does not go to ground/zero, it goes to one of the rails. The input DC current is tiny, especially JFET op-amps, but it is not zero. In this circuit there are several op-amp inputs that depend on the connected POT for a zero DC voltage reference including:
VR1 -> U2A
TP1 -> Q1
RV5 -> U1B
RV2 -> Q2
RV4A; RV4B -> U5A
TR5 -> U6A
This kind of thing is often not a problem initially but after some use, loud pops happen when the pots are adjusted. Each pot should have a ~10x shunt resistor that maintains a DC connection if the pot goes open.
There are some bias pots where pot failure will prevent the circuit working but none that will destroy parts, so mitigation is of limited value.
VR1 -> U2A
TP1 -> Q1
RV5 -> U1B
RV2 -> Q2
RV4A; RV4B -> U5A
TR5 -> U6A
This kind of thing is often not a problem initially but after some use, loud pops happen when the pots are adjusted. Each pot should have a ~10x shunt resistor that maintains a DC connection if the pot goes open.
There are some bias pots where pot failure will prevent the circuit working but none that will destroy parts, so mitigation is of limited value.
Barring pot failure you have lots of work to do. Clean it all up and re-post the real schematic - when you're not so busy 😊
I see what you mean. To be honest, these pots should never and normally be used fully "wiped" to ground (that is, with zero output). I could add a small value series resistor (0.1x the pot's resistance) going to ground so that opamp inputs are never both to ground. That would mean that input volume will never be zero, but that is not a problem really. But I don't think these pots would really be exposed to significant DC at any time, since most of the pots you pointed out should be at 0VDC or close to it (with few exceptions, eg. the pot before the NE5532 opamp, since they have some offset current that can be significant; the addition of a very large value capacitor would mitigate the issue, even though I would like to avoid this).
OK, so here are the screenshots from the LTSpice simulation (where everything appears to work correctly).
Keep in mind that I simulated switches with variable resistors (On = 1 ohm, Off = 1000Mohm or so). Transient simulation and AC simulation all yield the expected results (of course, I'm also using ideal opamps, for instance, therefore some issues won't rear their head here).
Keep in mind that I simulated switches with variable resistors (On = 1 ohm, Off = 1000Mohm or so). Transient simulation and AC simulation all yield the expected results (of course, I'm also using ideal opamps, for instance, therefore some issues won't rear their head here).
First off, this gadget will not be located in a reactor control room. It's an electric guitar effects pedal/preamp stage.
IOW, don't worry about the "pots". They are all legal in a guitar preamp scenario. Also, you are using weird R-values. Why? Most do not need to be 1%. 19.6K? 6.34K? The caps are probably going to be +/-10% or 20% 😕
IOW, don't worry about the "pots". They are all legal in a guitar preamp scenario. Also, you are using weird R-values. Why? Most do not need to be 1%. 19.6K? 6.34K? The caps are probably going to be +/-10% or 20% 😕
TP1 is simply an attenuator into the gate. It's there to accomodate different FETs. Depending on Vp, the incoming signal could be strong enough that the FET would always be overdriven, and it's there to ensure linearity at low gain (or sensitivity) levels.
The same applies to RV2. The opamp forcing the bottom leg of the resistor to be at 0.25V (or any other value) essentially rounds off the FET's response and makes it less hard-clipped on the positive (negative) excursion, IIRC. According to the simulation, it works. I took inspiration from some circuit I saw on the internet (which actually had no resistor between the opamp's output and the source; this forced the FET to swing only one way though, too intense a distortion effect for my purposes).
The resistor values are selected from the 1% series just for simulation purposes. I do plan on selecting resistors and capacitors anyway to ensure minimum deviation from the plotted AC response (frequency linearity) but it's not that essential.