hi i just wondering if somebody could give me a leg up on how to access the filter selection using windows serial port is ready to go, just not sure where to begin?
The scheme is only for RJ45. Check manual for I2S input requirements and check hifidurino if you need more help.
Here’s the link to the old discussion on synchronized operation in dam1021 again for the record: Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 Khz
Here a measurement of the jitter test signal of Arta.
Green is a analog loopback of the analyzer in/out. This can be considered as no jitter reference as the ADC and DAC of the analyzer are clocked by the same clock.
Red is the DAM getting its signal from the analyzer via SPDIF.
You see there is next to no difference.
You need an extreme zoom to see deviations
Moreover this is the "differential jitter" between the DAM and the analyzer clock. So the "culpid" of the jitter could analyzer clock if the DAM is more stable.
Green is a analog loopback of the analyzer in/out. This can be considered as no jitter reference as the ADC and DAC of the analyzer are clocked by the same clock.
Red is the DAM getting its signal from the analyzer via SPDIF.
You see there is next to no difference.
You need an extreme zoom to see deviations
Moreover this is the "differential jitter" between the DAM and the analyzer clock. So the "culpid" of the jitter could analyzer clock if the DAM is more stable.
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Sorry and last question and to the point what terminal program would the forum suggest to access umanager?
Just to avoid misunderstandings, the nonlinearity of the load is not an property of the VRef supply, but of the R2R network (when used like it is in the DAM).
Aha - tnx.
So depending what signal level the DAC is outputting, the resistance of the ladder varies?
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So depending what signal level the DAC is outputting, the resistance of the ladder varies?
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Resistance of ladder as seen by the vRef supply - ok!
Did you also check the output impedance linearity of the ladder - can't recall?
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Did you also check the output impedance linearity of the ladder - can't recall?
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The plot, as well as the output statement, are computed values of the resistor network, not measurements.
The output resistance assumes a 0 Ohm impedance of the VRef source. But the real value of the impedance of VRef is neglectable for the output resistance, it has some influence on the THD.
I did also a few measurements. They were conform with the computed values.
The output resistance assumes a 0 Ohm impedance of the VRef source. But the real value of the impedance of VRef is neglectable for the output resistance, it has some influence on the THD.
I did also a few measurements. They were conform with the computed values.