Replaced C633 (0.47uF / 50V) - no change, please see /RES video:
https://www.youtube.com/watch?v=s8mXo8sh5Pk
https://www.youtube.com/watch?v=s8mXo8sh5Pk
Pin 26 (PSW) is changing from 0 to 5V when power button pressed.
The /RES timing that you're seeing seems to agree with the service manual. I am surprised that the reset duration is so short (admittedly, I didn't initially notice the reset waveform diagram in the manual until you pointed it out). Such a short reset pulse doesn't give the +MB rail much time to stabilise following power-on. Trying a different C633 was worthwhile in case the original capacitor had begun to fail resulting in an even shorter reset delay. So it appears that CPU reset seems OK at this point.
The power switch generates a processor interrupt on INT1 (pin 26) which you have confirmed as working. However, as the CPU isn't yet operational and pressing the switch is unlikely to have any effect.
In your video, was the oscilloscope set on DC at 1V/div, or something else? Ceramic resonators can fail, although at this stage, cessation of oscillation after a while could be caused by the CPU as it executes a 'software reset' or sets its 'main clock stop bit' when executing unexpected ROM code. From the MC16C/80 datasheet:
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 0004 hex) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved.
Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006 hex). Switching to the sub clock oscillation as CPU operating clock source before stopping the clock reduces the power dissipation.
When the main clock is stopped (bit 5 at address 0006 hex=1) or the mode is shifted to stop mode (bit 0 at address 0007 hex=1), the main clock division register (address 000C hex) is set to the division by 8 ("08 hex").
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN -XOUT drive capacity select bit (bit 5 at address 0007 hex). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit defaults to “1” when shifting from high-speed or middle-speed mode to stop mode and after a reset. This bit remains in low-speed and low power dissipation mode.
Regarding the ROM address bus and data bus, all you need to verify with the 'scope is that you are getting clean transitions between logic '0' and logic '1'. Any line that sits mid-way between logic levels, or has excessive 'noise' on it, usually indicates a problem.
Out of curiosity, what happens (if anything) if you press the power button after power-up before the 1-minute mark?
Last edited:
Hi,
The reset pulse it is working like it suppose to by looking at the scope signal pulse. Did you check the reset pulse at the micro pin 19 or at the Q507 collector?
The reset pulse it is working like it suppose to by looking at the scope signal pulse. Did you check the reset pulse at the micro pin 19 or at the Q507 collector?
Hi,
There are 2 signal that we can check to see if the micro it is addressing the memory at the reset. One is the memory chip enable /CE and the output enable. The 2 must be set to zero to enable the memory. You can check it to see if you see pulses means that the micro it is communicating with the memory.
micro pin 69 -chip enable - memory pin 26
micro pin 63 - output enable - memory pin 28
Check both pin to see if they are pulsing.
There are 2 signal that we can check to see if the micro it is addressing the memory at the reset. One is the memory chip enable /CE and the output enable. The 2 must be set to zero to enable the memory. You can check it to see if you see pulses means that the micro it is communicating with the memory.
micro pin 69 -chip enable - memory pin 26
micro pin 63 - output enable - memory pin 28
Check both pin to see if they are pulsing.
There is also ROM /FOE = output enable (ROM pin 28), attached to the CPU /RD (pin 63). This is active low during ROM reads.
It was DC, but not completely sure on Voltage scale (not yet figured that out). My DMM says it is 2.45V DC.
I didn't notice any difference between power-up before and after "deadline".
Well, I'll try to investigate more today-tomorrow. Will look for something unusual and will do more checks on ROM signals.
Do you know guys what are my chances to find a proper firmware for this unit? A quick search in the google didn't give me much.
Sorry, haven't seen couple more replies 🙂
Here's what I'm going to try today. More checks/suggestions are very welcomed!
1. uP pin 69 CS0 <chip enable> /FCE - IC527 ROM pin 26 /CE
Check for pulsating signal.
2. uP pin 63 /RD <output enable> /FOE - IC527 ROM pin 28 /OE
Check for pulsating signal.
Well, I actually checked that on one of PCB checkpoints marked /RES.
But shouldn't I see pure oscillations even in DC mode? Per service manual, it have to be sin(x) alike signal with 62.5 ns period and about 1.2V average. What I actually see is just small-aplitude oscillation around 2.45V.currentflow said:
Here's what I'm going to try today. More checks/suggestions are very welcomed!
1. uP pin 69 CS0 <chip enable> /FCE - IC527 ROM pin 26 /CE
Check for pulsating signal.
2. uP pin 63 /RD <output enable> /FOE - IC527 ROM pin 28 /OE
Check for pulsating signal.
Hi,
When your are looking a logic signal output make sure the zero = .5v and the high = 3.0 to 4.8v. Anything else will be a suspect bad signal. If /CE and the /OE are pulsing then the next thing to do it is to check all the 16 data bits going out of the memory to the micro as "currentflow" recommended in thread 42. It is possible that they stop pulsing then you need to turn ON/OFF the amplifier to scope the data pins. You need to scope all 16 data pins from the memory.
When your are looking a logic signal output make sure the zero = .5v and the high = 3.0 to 4.8v. Anything else will be a suspect bad signal. If /CE and the /OE are pulsing then the next thing to do it is to check all the 16 data bits going out of the memory to the micro as "currentflow" recommended in thread 42. It is possible that they stop pulsing then you need to turn ON/OFF the amplifier to scope the data pins. You need to scope all 16 data pins from the memory.
AC 240V was applied during the beginning of each video. Notice constant signal at the end - it refers to stop oscillating state.
1. uP pin 69 CS0 <chip enable> /FCE - IC527 ROM pin 26 /CE
https://youtu.be/PSAfroP49SQ
2. uP pin 63 /RD <output enable> /FOE - IC527 ROM pin 28 /OE
https://youtu.be/ROTLqs86Tno
The below one is typical for D0-D10 data pins
3. uP pin 122 D0 FD0 - IC527 ROM pin 29 Q0
https://youtu.be/r8EBGkLlTKE
The below one is typical for D11-D15 data pins. The most confusing signal for me
4. uP pin 103 D14 FD14 - IC527 ROM pin 43 Q14
https://youtu.be/VwkDkLnVCDM
1. uP pin 69 CS0 <chip enable> /FCE - IC527 ROM pin 26 /CE
https://youtu.be/PSAfroP49SQ
2. uP pin 63 /RD <output enable> /FOE - IC527 ROM pin 28 /OE
https://youtu.be/ROTLqs86Tno
The below one is typical for D0-D10 data pins
3. uP pin 122 D0 FD0 - IC527 ROM pin 29 Q0
https://youtu.be/r8EBGkLlTKE
The below one is typical for D11-D15 data pins. The most confusing signal for me
4. uP pin 103 D14 FD14 - IC527 ROM pin 43 Q14
https://youtu.be/VwkDkLnVCDM
Hi,
In the last movie looked like the signal for bits D11-D15 are high all the time like if they are floating. Now the question is Does the program used does bits or not?
In the last movie looked like the signal for bits D11-D15 are high all the time like if they are floating. Now the question is Does the program used does bits or not?
Hi,
I would like that somebody collaborate what I found. In the service manual the picture showing the frequency it is about 1 division = 50 ns + more less 10nsec that is = 60 nsecs. 1/60 = 16.6mhz. In the video showing the amp frequency it is about 1oonsec or 1 div= 100ns. Means that the amp clock it is running at 10mhz. Can somebody double check if this is correct.
I would like that somebody collaborate what I found. In the service manual the picture showing the frequency it is about 1 division = 50 ns + more less 10nsec that is = 60 nsecs. 1/60 = 16.6mhz. In the video showing the amp frequency it is about 1oonsec or 1 div= 100ns. Means that the amp clock it is running at 10mhz. Can somebody double check if this is correct.
I'd say that on video XL501 signal period is less than 1 division, more like ~60-65ns which is about right.
Sorry, 100ns is the limit for my scope...
Sorry, 100ns is the limit for my scope...
And by the way, replaced 5V voltage regulator and it didn't help. Going to get 16MHz resonator and try that either.
The service manual shows exactly 4 complete clock cycles in 250ns. 250/4 = 62.5ns = 16MHz.
From the video, paused at 5 seconds, I can count 11 cycles in 700ns (7 divisions). This is about 63.6ns period, or 15.7MHz. Given that we don't know how well the 'scope has been calibrated and that it isn't synchronising very well, I would say it's certainly in the right ballpark.
Hi,
To currentflow: Thank you for double check my finding. I did what you did by stopping the video and count one cycle. The problem was that he is using 100ns per division. Maybe that was what I did wrong.
To currentflow: Thank you for double check my finding. I did what you did by stopping the video and count one cycle. The problem was that he is using 100ns per division. Maybe that was what I did wrong.
My pleasure. It's best to count as many complete cycles as possible in order to minimise the reading error.
The first three videos show clean transitions and look normal. However, the fourth (data bus high byte) tends to indicate some bus contention. In other words, more than one signal on the bus is attempting to assert its logic state at the same time. Can you confirm that the PCB is free of contaminants and that there is no evidence of previous liquid spillages near the traces or ICs?
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