I am planning to build the following AD1865 and cs8416 schematic from pavouk.org because it includes toner transfer pdf's and this makes it really easy.
CS8416 S/PDIF decoder
AD1865 based audio DAC with I2S input and voltage output
Does anyone have any comments on the quality of layout and circuit?
I intend on using Salas regulators and C0G ceramics instead of x7r
Thanks
CS8416 S/PDIF decoder
AD1865 based audio DAC with I2S input and voltage output
Does anyone have any comments on the quality of layout and circuit?
I intend on using Salas regulators and C0G ceramics instead of x7r
Thanks
1) I notice that the S/PDIF input transformers don't appear to have a D.C. blocking capacitor in series with their primaries. Unless you are sure that your transport's S/PDIF output signal contains no D.C. component, this omission may be distorting (adding jitter to) the received signal.
2) I have some experience with the AD1865 in the Vout configuration. While the sound is okay that way, in my opinion, it's much better in the Iout configuration via a passive resistor I/V (of as high as 330 ohms). The resulting signal voltage can be A.C. coupled (without an intervening active stage) to your linestage input.
2) I have some experience with the AD1865 in the Vout configuration. While the sound is okay that way, in my opinion, it's much better in the Iout configuration via a passive resistor I/V (of as high as 330 ohms). The resulting signal voltage can be A.C. coupled (without an intervening active stage) to your linestage input.
Thanks for the reply Ken.
What value for the capacitor do you suggest?
Pavouk has a schematic for AD1865 with Iout.
Audio DAC with AD1865
I guess i can build both and choose the one that i like best.
What value for the capacitor do you suggest?
Pavouk has a schematic for AD1865 with Iout.
Audio DAC with AD1865
I guess i can build both and choose the one that i like best.
10nF to 100nF should be fine for coupling the S/PDIF transformers. Ideally, caps. featuring low parasitic inductance, such as SMD ceramics, are to be preferred since this signal is wideband. Although, I've used both 22nF NP0/C0G ceramics and 10nF film & foil polypropylene with equal success. I must add that I've not before seen a paralleled dual transformer configuration utilized here, I assume there must be a good reason the designer chose to do so. Perhaps, it's an attempt to produce a composite transformer having a wider bandwidth than either one alone, I'm not sure.
The Iout schematic appears fine to me. All one would need then do is A.C. couple (via a quality capacitor) the resulting signal voltage to a linestage. The DAC signal should be large enough that not much gain would likely be required while the output impedence would be just under 200 ohms, together eliminating the need for the usual DAC active output stage.
The Iout schematic appears fine to me. All one would need then do is A.C. couple (via a quality capacitor) the resulting signal voltage to a linestage. The DAC signal should be large enough that not much gain would likely be required while the output impedence would be just under 200 ohms, together eliminating the need for the usual DAC active output stage.
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Single sided design is going to be a compramise, best thing you could do is etch it on double sided PCB material and have a complete ground plane on the other side (clearing where throough holes come through)and wire link ground pins to this plane. The good thing about this design is it allows for this, and would be greatly improved as a double sided layout.
Thanks everybody for your suggestions.
Creating a double sided version with a ground plane is a very interesting idea (and easy enough for my amateur level).
Creating a double sided version with a ground plane is a very interesting idea (and easy enough for my amateur level).
I'm finding these double sided PTH boards excellent for building DIY DACs on. The pads don't lift off when resoldering, they're nicely robust and due to being PTH both sides are usable for SMT components. Makes for very compact layouts 🙂
2X Double Side Prototype PCB Board 5x7 cm Tinned Universal Board FR4 | eBay
2X Double Side Prototype PCB Board 5x7 cm Tinned Universal Board FR4 | eBay
With this design there's going to be inevitably a lot of jitter, the cs8416 spdif plus the glue logic...
Did you see the iancanda board at the top of the page, its ideal for AD1865 because it does the delay/conversion and synchs the clocks for you with the lowest jitter possible also would allow the option to try other R2R chips in NOS mode with protoboards like the one abraxilito posted (I just ordered 4 of those they look great.)
Did you see the iancanda board at the top of the page, its ideal for AD1865 because it does the delay/conversion and synchs the clocks for you with the lowest jitter possible also would allow the option to try other R2R chips in NOS mode with protoboards like the one abraxilito posted (I just ordered 4 of those they look great.)
Not really worth worrying too much about jitter - I don't find it a problem in terms of the subjective SQ when running multibit DACs. Definitely though its an issue on S-D DACs. Rather worry about reducing noise modulation, that's the biggest detractor from SQ.
What do you think about this schematic, is it worth adding the extra noise to align the channels ?
You mean is it worth adding a long shift reg? I doubt I'd bother - the delay of one sample I don't think is audible. I would though on that circuit prefer to run the HC logic at 2.5V rather than 5V. If you added an HEF4517 to do the shifting, I doubt that would add much noise though, being 4000 series, the slowest known CMOS 🙂
Yes that's what I meant, I can hear the delay with headphones. One thing I'm not sure of in these schematics is he calls for 24 bit I2s, but most I2S output USB stuff use a 256x clock. I think its a gotcha if anyone is planning on using these with a usb-i2s device.
So the optimal voltage for 74HCT164 in that circuit is 2.5v. Can you explain why? Sorry, im kinda clueless 😀
You mean is it worth adding a long shift reg? I doubt I'd bother - the delay of one sample I don't think is audible. I would though on that circuit prefer to run the HC logic at 2.5V rather than 5V. If you added an HEF4517 to do the shifting, I doubt that would add much noise though, being 4000 series, the slowest known CMOS
A design goal of Pavouk's DAC is 192K operation. The HEF4517 is too slow, as Pavouk found out. At 2.5V the HC164 is not fast enough, either. Besides, shifting the data will have little impact on sample clock jitter. Even though BCK is driving seven loads, it is of little consequence. With the AD1865, the low-going latch edge updates the respective DAC output. Most other DACs update on a rising BCK edge.
That's interesting to know could this be one reason why the AD1865 is more popular than the seemingly identical the PCM56k/PCM58k
Its not HCT, that wouldn't work at 2.5V, its HC. As Tam Lin has pointed out that 192k operation was desired by the originator, then he might indeed be correct about the speed of the HC164 not being sufficient at 2.5V; however I'd not recommend running a DAC at 192k. Its throwing away some of the advantage of using the AD1865 to run it so fast and there's no audio benefit, only detraction of running at such a high SR.
The reason to reduce the supply is to keep the power supply noise low as noise is enemy no.1 to decent sound. The edge speeds reduce nicely at such a low supply voltage.
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