Has anyone seen this front-end before?

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the main culprit was an inductor in a parallel path (to smooth out the 2nd woofer impedance peak to make the xo work at all).

Beware , if this inductor is DC coupled and even if the amp
has very low output DC offset there will be significant DC
current flowing through this inductor.

If its DC impedance is let say 1mR and that the amp has 10mV
output offset this can induce as much as 10A DC current
if the amp has low enough output impedance , wich is systematicaly
the case at DC with high NFB amps.
 
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Read this Heavy Load: How Loudspeakers Torture Amplifiers | Stereophile.com

If you are designing an amp that you would be happy to connect to ANY commercially available loudspeaker, I am afraid you have to accept that most of those designers don't really care - in fact, I think to test they just take a DVM and measure the ohms across the terminals (well, not quite, but you get my drift).

I think 10A peak output current capability for a 200Watter is the minimum. But, like a lot of things, this really is in the hands of the designer, and we have to allow a lot of lattitude here for different interpretations. :)
 
My amp is designed to deliver 30A and 250W into 4 ohms.

Interesting. 250W in 4ohm means about +/-50V peak into a 4ohm load, or +/-12.5A peak. If you can drive 30A peak, then you can drive 1.7ohm loads (about the Wilson Puppy). Then why are you complaining?

Can you show the distortions vs. load dependency?

Have you checked the worst case SOA for 4 pairs? I think you would need at least 5 pairs, 6 would be better... And then, have you considered the impact on stability of a 4"-5" length of the power devices layout, with all the involved parasitics? You need to define the PCB layout, before even attempting to evaluate the output stage AC HF behaviour.
 
Okay, I'll show you something: Please have a look here and here.
Now it's your turn. :D

Sorry, I was not born in the 70's and don't know what a tape recorder is.

Here is one of mine, about 10,000 mosfets on the analog side (including analog switches and CCDs).

Let me know when you have something (with discretes) belonging to the 21st century.
 

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Well , your design is about 3.2R mini impedance that can dip
below 1R according to your numbers due to magnetic saturation
but then what will be the max current once your LCR network
is adapted ?..
Our student trainee will hopefully complete the new xover boards by tomorrow, then it's time to measure (and listen) again... we also advised him to arrange the component layout to avoid any magnetic coupling between the various coils -- by actually measuring in search for minimized coupling before mounting (again an issue that is often seen even in professional high-end speakers).
 
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Our student trainee will hopefully complete the new xover boards by tomorrow, then it's time to measure (and listen) again... we also advised him to arrange the component layout to avoid any magnetic coupling between the various coils -- by actually measuring in search for minimized coupling before mounting (again an issue that is often seen even in professional high-end speakers).

Is that Waly by any chance? :D
 
Output speed?

Any one still remember Edmond's front end ;)
Well I still need an OPS for it and I have a question.
How close to minimum phase is a BJT near Ft?

In the LTSpice help they call TF the "transit time"
If it is a real time delay then behaviour near Ft will depart from minimum phase.
If TF is just the time constant of the frequency roll-off then it will be close to minimum phase.
So a second question would be -
How close is SPICE to real transistor behaviour in this area?

This puts an upper limit on loop stability so it's fairly important for optimized compensation.

Best wishes
David
 
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Hi David,

Did you read these comments , where I stated that a clear distinction should be made between time delay and phase lag? Or is it just a coincidence? ;)

As for your question, you can figure it out by observing the delay in onset of a step response. BTW, "transit times" as published in most data sheets are not very helpful, because the tranny is used as a switching device, thus not as a linear amplifier, which makes a large difference (comparable to TTL vs ECL logic).

Cheers,
E.
 
Hi David,

Did you read these comments , where I stated that a clear distinction should be made between time delay and phase lag? Or is it just a coincidence? ;)

No, just a coincidence. I did not ask in the context of feedback at audio frequencies, as in your discussion, I know that stuff. I am interested in how far the unity crossover frequency can be increased. There is a clear difference between a minimum phase roll off, that can be equalized, and a time delay, that can't.
A pity that Bob Cordell uses the term "excess phase" rather loosely in his book. It would have been a chance to present a concept that is so frequently misunderstood, as your link shows.
Dennis Feucht wrote an article that seems to imply transistors are not minimum phase near Ft. Since he seems pretty sharp I take it seriously.

As for your question, you can figure it out by observing the delay in onset of a step response.

An ONsemi NJL4*** has 35 MHz Ft so it would need nanosecond resolution to be accurate. Equipment to do measurement at that speed is not DIY level. I hoped some of the people here who do electronics professionally would have the information.

Best wishes
David
 
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But you may figure out how a simulator deals with it, i.e whether it's treated as phase shift or as propagation delay.

To determine what SPICE does I plan simply to plot the frequency response and compare the phase with the amplitude slope. I am a Bode kind of bloke;) But I still need to know what a transistor really does.

Best wishes
David
 
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