I don't like leaving the open loop gain undefined, at the mercy of the opamp, in particular when there's no performance penalty involved.
Also, with today's wideband opamp it is important to keep the asymptotic frequency response under control; considering the PCB parasitics, it won't take much to get a 500MHz oscillator. R9 will help defining the asymptotic frequency response. Of course, for rather slow opamps like the OPA134, this is a moot point.
There is also a PSRR impact. Increasing R9 makes the PSRR peak (as a function of frequency). Decreasing R9 decreases the PSRR but flattens the frequency dependency and also decreases the sensitivity to stray effects (parasitics, etc...). 100-500k is nothing but a good compromise.
What's that? With the cap in parallel I don't see how such a large resistor could have an effect on HF stability.
Samuel
Caps are caps only in simulators. In the real world they have series inductance and they self resonate when you expect less. One good reason to go for SMD.
Sure, but this still does not explain a positive effect of the parallel resistor. At HF it won't be a nice pretty 100k resistor either.
BTW, do you have any data on the BF862 noise performance within the audio frequency range? Does it come close to the 2SK170?
Samuel
Whatever series inductance the 100k would have, it will be greatly amortised. But anyways, R9 is more a matter of design style and playing safe. BTW, the compensation you are using in your original schematic leads to a 10MHz unity loop gain. Quite high in my book, it may or it may not be stable, greatly depending on the PCB layout.
BF862 is slightly better (certainly not worse) than 2SK170, whent it comes to noise. The big advantage is the x7 lower Ciss, for the same transconductance. And of course the price, BF862 sells for pennies.
Hi Scott
Wouldn't a MAT02 front end still beat the snot out of a FET AD823 for low impedance noise meas. of a PS?
I get 4.8 MHz (33 pF and 1k). The design is tested and stable.
What's its 1/f corner? Datasheet just quotes voltage noise at 100 kHz which is of little help.
Samuel
I measured only a very few (so no statistics available) with the corner frequency around 300Hz.
Ok, for 1k and 33p and a closed loop gain of about 1k/40ohm=25.
6.7MHz unity loop gain and 38 degs phase margin. Could be stable in your implementation, but not something I would place my bets for stability (or recommend without specifying the PCB layout).
Attachments
Thanks, that's good info. At what drain current?
It is a current-feedback architecture so closed-loop gain does not figure in a first-order estimate of loop gain. Loop gain is simply given by the compensation capacitor and the feedback resistor.
How did you do that sim? For these topologies it is important to consider the actual closed-loop gain even though it is a current-feedback architecture (impedance at the inverting input is relatively high because of finite gm of the input transistor, so closed-loop bandwidth reduces considerably at high closed-loop gains). As far as I remember real-world tests showed a transient response which suggests more than 38 degree phase margin.
Samuel
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About 9mA.
It's of course a current (at the input) voltage (at the output) feedback loop. Using a standard Tian probe to evaluate the loop gain as per the attachment.
The simulated closed loop gain is close enough to the quick ballpark. According to the simulations, it is the closed loop bandwidth that is 4.8MHz. The CL bandwidth has little to nothing to do with the ULG frequency and the phase margin.
But anyways, 4.8MHz or 6.7MHz, at such frequencies, unless the PCB layout is optimized, the phase margin is usually defined by the parasitics rather than the lumped elements. Parasitics may increase (or decrease) the phase margin.
The step response of a 100KHz signal doesn't look that great, see the attachment. But beyond absolute values, the circuit is certainly not a first order system.
Attachments
Yes, I planned a double MAT-02 version but it is only good for lowish impedance sources. The FET version can do just over 1nV and the 2XMAT-02 can be coaxed down to .6nV with care.
That circuit was a cute way to use only a dual transistor and dual op-amp to make a true in-amp. The classic Demrow/Cohen instrumentation mic preamp is tried and true as is the SSM2019 😉 Seventh Circle Audio sells some kits with decent parts.
To evaluate loop gain of the global feedback loop you'd need to place the probe after C3.
I don't see anything wrong with it. Overshoot is small enough to indicate sufficient stability margin, and it is anyway of no concern to measure noise and swamped by the following low pass filter.
Well, it's absolutely no problem to lower it--simply increase the compensation capacitor.
Show me one which is... It's all a matter of preference. You prefer to put efforts into a super-dupy-low-noise regulator because the amplifier has poor PSR; I prefer a circuit with high PSR and long battery life.
Samuel
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Thanks Scott for pointing to this SSM preamp part. I new about INA parts before and after looking about the web, there is THAT corp is doing alot in this area as well.
The SSM2019 looks like a nifty little part. If it uses a similar MAT-02 macro then there is not really any reason for me to go with a transistor array? Is the MAT-02 discontinued for commercial products or any thing else to replace them?
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Sorry, but I disagree. For multiloops having a common node at the output you need to break all loops to get the loop gain. See e.g. http://www.ece.ucdavis.edu/~hurst/papers/FullyDiffRR,CAS.pdf
Not that easy... Increasing the cap value actually increases the ULG frequency!
I agree, this is, at the end of the day, not an oscilloscope input stage.
No it doesn't have a poor PSRR, check again the schematic. For a gain of 60dB the PSRR is about -30dB, which is pretty good. The noise cancelling power buffer is required only for the ultimate noise performance (around 0.3nV/rtHz).
My SSM2019 amplifier measures 1.7nV/RtHz at A=100, 5.6nV at A=10 and 1.5 at A=1,000. So it's a tad worse than the datasheet at the very high gain, but this is probably due to cabling and capacitors -- I'll bet the folks at ADI used a Quan-Tech 5173 to do their measurements. The SSM is a $4 part at DK and gain is set with one resistor.
Just for a reality check here -- the noise from a Jung regulator with an AD797 should be in the very low tens of nano-Volts, so a six-sigma standard deviation puts the SSM2019 in contention. (WJ indicated that the original SSM2017 100X amplifier had noise of 2.6nV/RtHz). You can also root square subtract the amplifier's noise, but purists may object...
Wow that has got be one of the best deals in audio today. Is that for a DIP package too.
I wonder where the gain setting is optimum for one the modded Panasonic capsules for low SPLs to midland SPLs? from the chart I would of guessed G= +10. hmmm...but your data says there are other variances from part-part?
I don't have time to look at the paper in detail but this would suggest that for a valid analysis we'd actually need to dig into the opamp and place the probe inside its Miller loop. What's the phase margin of your opamp model BTW?
Because there is more local feedback of the opamp--the ULG of the global feedback loop surely decreases. And we know that the opamp is unity-gain stable so this is not much of an argument. As I said earlier in this thread the use of Ahuja compensation (i.e. including the cascode within the Miller compensation loop) opens the possibility for local instability of the compensation loop. But it works well in this particular case--the bandwidth of the cascode must be at least an order above that of the opamp. And it just increases PSR so much...
I presume this is RTO and not RTI..? At which frequency?
Samuel