100W Ultimate Fidelity Amplifier

[still4given]

This is what I'm seeing.

The sine wave is at less than 1V output. The square wave is barely on because any more it will go into complete oscillation.

 

[sonal kunal]

Can check connection between [R5, R3, and C6] and [R4, R6, and C8] those were missing in last image you post.

I should also build and check on strip board I have all parts required.

 

[still4given]

Hi Sonal,

Good catch. I had fixed the connection from R5 but missed the one from R6. Unfortunately I just connected it and not the bias is way too high. This circuit doesn't have a pot to adjust that. I'm not sure where to insert that but it looks like it needs it.

Blessings, Terry

 

[c08bm]

D3, D7 and D8 should be on heatsink, I'm pretty sure you can set bias from R16, try lower in your case

 

[sonal kunal]

Like c08bm said you can use 50R trimpot instead of R16 but D3, D7 and D8 should be on heatsink. Because of your layout other way around will be removing R16 and using trimpot parallel with D3. Just wire timpot to increase resistance when turned CW.

 

[still4given]

Like c08bm said you can use 50R trimpot instead of R16 but D3, D7 and D8 should be on heatsink. Because of your layout other way around will be removing R16 and using trimpot parallel with D3. Just wire timpot to increase resistance when turned CW.

If that's the case, thermal transfer might be a good alternative. Which way on R16 reduces bias? Lower value or higher?

 

[sonal kunal]

If that's the case, thermal transfer might be a good alternative. Which way on R16 reduces bias? Lower value or higher?

Lower value will decrease bias. I'll suggest remove R16 and and solder resistor with lower value underneath D3. That way you will have better thermal tracking because of forward voltage drop from D7, D8 when temperature rises.

 

[still4given]

Wow, I typed that from my tablet and didn't notice that it translated "Thermal Trak" to thermal transfer. With ThermalTrak outputs D7 & D8 would be on the heatsink already. If I can get this working and it sounds good I may try to do a layout for the TT transistors. I'm going to try lowering the bias right now and I will report back.

Blessings, Terry

 

[still4given]

OK, I just tried paralleling a 100R pot with R10 and even at it's lowest value, R16 = 0.1R I still have 300mA bias and that is with the light bulb tester in place which is reducing the rails to 7V. Without the light bulb I'm sure I would have blown fuses. Something is not right. Has anyone tried the spice file I made? If I can get that working I will at least have a working circuit to compare to.

Thanks, Terry

 

[sonal kunal]

Can you post voltage reading at opamp output, between R3-R5, R4-R6 and voltage across D3, D7, D8.

Lots of software were uninstalled for windows 10 upgrade. I better re-install multisim to simulate A4.

 

[still4given]

I don't think it will help because with the bias so high the rails are only +-7v. I suppose I could try lifting a leg on R29/R30 so I can run the front end.

 

[still4given]

Can you post voltage reading at opamp output, between R3-R5, R4-R6 and voltage across D3, D7, D8.

Lots of software were uninstalled for windows 10 upgrade. I better re-install multisim to simulate A4.

I had to pull the IC to get the rails high enough to activate the zeners. I didn't go much higher for fear of burning something. Attached is a marked up schematic

 

[Nagark]

Hello sir here are the files also the reference schematics I use, I did some changes on the layout for my self but you can use the schematic and change some values of the AX-20P to be the original values from AX-20P schematic, I spend a couple of day already checking for error or better say "bugs" and I have not found any more so far, if you guys see any error let me know so I can fix it right away I said this because eyes get tired man

ok here are the files

Regards
Juan

Hi Mr.Juan u can share de sprintlayout files ? because i need to do some change for my needs

 

[sajti]

I had to pull the IC to get the rails high enough to activate the zeners. I didn't go much higher for fear of burning something. Attached is a marked up schematic

I would short the anode of D3 with the cathode of D8, to set the output stage to classB. This can be a good intermadiate step to test the basic work of the amplifier.

Sajti

 

[vargasmongo3435]

Hi Mr.Juan u can share de sprintlayout files ? because i need to do some change for my needs

Hello sir here is the Sprint file

note: is for Sprint Layout 6 version

Regards
Juan

 

[still4given]

I would short the anode of D3 with the cathode of D8, to set the output stage to classB. This can be a good intermadiate step to test the basic work of the amplifier.

Sajti

Doesn't that just short the VAS?

 

[still4given]

I don't think this circuit works. Try as I may, I can't get it to work in LtSpice. I simmed the output section with a different IPS and I works so it is in the front end somewhere. I'm setting it aside until Mile finds his way back here.

 

[Nagark]

Hello sir here is the Sprint file

note: is for Sprint Layout 6 version

Regards
Juan

Thanks

 

[sajti]

Doesn't that just short the VAS?

No. It short the bias network only.

Sajti

 

[gaborbela]

These post will be off topic! I only post here because there are several people here who design or draw PC boards layout.
I would need something like the attached power supply board but with 2 pair capacitor and CRC mode.
Also it would be good if I could use MUR860 diodes. No fuse needed on the board..

If someone know similar design on the forum already exist please let me know
Thank you very much
I tried with Sprint 6 and just wasted a couple hours with out any good result.

Greetings