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Old 2nd June 2009, 05:18 PM   #1
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Default Return of my differential VAS

Ok, I said that I would not post on this again until I actually built one and tried it out. So I did. This is a work in progress and I’m sure a couple of warts will show up and there is some tweaking to do. Hopefully I’m not missing anything fatal .

This is what I like to think of as a signal path based on pair-wise matching rather than absolute parameters. I was able to strip out a lot of components from the original circuit. The self biasing FET input lights up the whole thing at about 5mA a leg, the bipolars were pulled right out of the bin without matching (though they are from one lot). The bipolars basically make up a CMCL and differential VAS at the same time. Returning C1/C4 to ground greatly improves PSRR. I used an LME49600 as an output stage for simplicity this time (thanks Sigurd). You can vary R1-R5 for different input gm, bias, and linearity. The 2K resistors “sop up” random offsets, without them the DC solution is singular somewhere for any offset voltage on the diff-pairs. You can also probably get away with Q3 and Q8 as 1N4148’s as well as varying the VAS bias via their associated resistors.

In a second post there is a picture of a simple test circuit (to magnify the input error signal) and a scope photo. Excuse the cell phone pic and ignore the top trace. The picture is a DC crossplot of the input error vs output voltage with a scale of 2V per div horizontal and 20uV per div vertical. That means one box is an Aol of 10^6 so here we have ~5X that. Even with a several percent FET mismatch I was able, with the two trims, to trim both offset and gain to near perfection. Interesting to note the 2k resistors do not effect Aol which could be trimmed from plus a lot through “infinite” and out again to minus a lot. I have not done exhaustive testing but it appears that there is also a very strong null of THD and it remains to be seen if all three are coincident. In the end it does not matter if the Aol is “infinite” at the same point that the THD is minimum. Of course everything drifts around and some kind of thermal attachment of the pairs is needed.

Not pictured is a quick test as a 20dB stage driving 100 Ohms || 1000pF. The +-15V .5A lab brick that I was using did not look pretty so no final THD until I get a new supply, but everything looked “eyeball” OK (no oscillations or overdrive problems) even at 24pF on all 4 comp caps. Glen, I tried a full 10% mismatch on C2/C3 and no “VAS’s gegen VAS’s” just a tiny increase in seconds. This BB is fully socketed BTW so it is a bit of a mess. I was actually surprised at the 1000pF being almost invisible here.

Well, so what? For one virtually all non-linear device capacitances/conductances are reduced (or made common mode errors) by first order by subtraction, no cascodes and their biasing needed . A fairly low device count to get an almost ideal gm/C transfer function as well as PSRR highly enhanced by the symmetry.

As an additional note you can bootstrap the bottom of C1/C4 ala the 797 and achieve the same output stage distortion removal. This is a little harder to in this case since you need pick off the input-output voltage of the buffer.
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Old 2nd June 2009, 05:22 PM   #2
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Picture of DC input/output transfer function.
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Old 2nd June 2009, 05:28 PM   #3
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Scott,

Nice job.........move over Mr.Curl. ( I am going to be beat up for this.....sorry Mr.Curl)

Does the active load / mirror help the distortion much or can it be dispensed with.

Keep up the good work we need more of this stuff.

Regards,
Jam
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Old 2nd June 2009, 05:36 PM   #4
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I could envision resistive loads, but I'm not sure of the performance.
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Old 2nd June 2009, 05:39 PM   #5
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Looks quite perfect.
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Old 2nd June 2009, 05:41 PM   #6
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Quote:
Originally posted by scott wurcer
Picture of DC input/output transfer function.
Any scale?
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Old 2nd June 2009, 06:07 PM   #7
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2V per div horizontal and 2mv/100 verticle . If the trace stays +- one div it's 10^6. This is just Aol, kind of an exercise.

Jams - first look via sim it still works pretty well with resistive loads but I think the PSRR will suffer.
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Old 2nd June 2009, 06:49 PM   #8
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very nice
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Old 2nd June 2009, 07:19 PM   #9
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Congratulations Scott! I would bolt all FETS together and put the whole thingy in a freezer, then in a kitchen oven, to get a clear drift picture.
Now you need a linearized output stage. No need for huge input resistance, let it be just flat and linear: do you need an infinity DC gain for audio? Also, you may sacrifice output voltage capabilities in order to bootstrap emitter followers. One way I would consider, is a feed-forward bootstrap by a JFET on top of BJT, with gate connected to base.
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Old 2nd June 2009, 07:40 PM   #10
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Thanks Scott very nice
And no “VAS’s gegen VAS’s”
It’s a very impressive circuit.
Could you post the values on the R1-R5?
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