The best way to stimulate the power supply and observe MOSFET parasitic oscillation (which gatestoppers prevent), is to apply a full-amplitude square wave load with very fast risetime and falltime.
Buy yourself a couple of (4 ohm) and (8 ohm) high wattage load resistors. Although they are intended to test amplifier outputs, they will do nicely for your supply testing work.
If you connect an 8 ohm resistor in parallel with a 4 ohm resistor, that combo will draw 4.5 amperes from a 12 volt power supply. Just what you want. You can fool around with the arithmetic to discover suitable combinations for testing a 5V supply and/or a 3.3V supply as well. Then you can buy the appropriate set of load resistors in a single order with a single shipping fee.
Build a little circuit on a stout piece of perfboard to drive the load resistors. The wonderful ST Microelectronics (STP27N3LH5) has just the specs you want: 30V, 27A, 0.02 ohms, 45 watts, 4.6 nanoCoulombs.
To calculate the MOSFET's power dissipation, recall that it operates in 3 different modes during the square wave:
In order to deliver the 4.6nC of gate charge and achieve fast risetimes and fast falltimes (<60 nsec), I calculate that you'll need a gate driver IC whose peak current is 2.5 amps or more. The (Micrel MIC4425) or the (Microchip MCP1407) would do the job nicely. As would dozens of other low side MOSFET driver chips.
You'll feed a 50% duty cycle square wave to the gate driver. This can either come from your function generator, or from a little square wave oscillator made from a CMOS 555 timer chip, a 10nF capacitor, and a 100K potentiometer. You could build the whole shebang on a single PCBoard: oscillator, gate driver, MOSFET+heatsink. With off-board connections using high current "FastOn" blade-shaped connectors. +12V, GND, PwrResistorPlus, PwrResistorMinus. Boom, simple.
Buy yourself a couple of (4 ohm) and (8 ohm) high wattage load resistors. Although they are intended to test amplifier outputs, they will do nicely for your supply testing work.
If you connect an 8 ohm resistor in parallel with a 4 ohm resistor, that combo will draw 4.5 amperes from a 12 volt power supply. Just what you want. You can fool around with the arithmetic to discover suitable combinations for testing a 5V supply and/or a 3.3V supply as well. Then you can buy the appropriate set of load resistors in a single order with a single shipping fee.
Build a little circuit on a stout piece of perfboard to drive the load resistors. The wonderful ST Microelectronics (STP27N3LH5) has just the specs you want: 30V, 27A, 0.02 ohms, 45 watts, 4.6 nanoCoulombs.
To calculate the MOSFET's power dissipation, recall that it operates in 3 different modes during the square wave:
- 48% of the time: OFF. Power = V x I = 12 x 0 = 0 watts
- 48% of the time: ON. Power = I x I x R = 5 x 5 x 0.02 = 0.5 watts
- 4% of the time: SWITCHING. Power = V x I = 12 x 2.5 = 30 watts
- Average power = (0.48 x 0) + (0.48 x 0.5) + (0.04 x 30) = 1.44 watts
In order to deliver the 4.6nC of gate charge and achieve fast risetimes and fast falltimes (<60 nsec), I calculate that you'll need a gate driver IC whose peak current is 2.5 amps or more. The (Micrel MIC4425) or the (Microchip MCP1407) would do the job nicely. As would dozens of other low side MOSFET driver chips.
You'll feed a 50% duty cycle square wave to the gate driver. This can either come from your function generator, or from a little square wave oscillator made from a CMOS 555 timer chip, a 10nF capacitor, and a 100K potentiometer. You could build the whole shebang on a single PCBoard: oscillator, gate driver, MOSFET+heatsink. With off-board connections using high current "FastOn" blade-shaped connectors. +12V, GND, PwrResistorPlus, PwrResistorMinus. Boom, simple.
I love it when you say "simple". I will have to think how to put that together.
Your suggestion of driving the power supply with a square wave reminds me of the discussion in snaa045a (pg 14 and 15) which is where I got the point I posted in #121.
I knew I would regret not getting the scope model that included a function generator as well. Regarding this, previously you had described a methodology for calculating the inductance of a transformer with a signal generator. I had asked in the context of modelling the in-rush of this power supply. How critical is measuring the inductance of the two transformers I intend to use? Can I get by without doing so? In other words, will I have to bite the bullet on a signal generator anyway and hence I may as well ensure whatever I buy can do square waves.
As I am stubborn, or rather just really want to see if this MOSFET series pass regulator can indeed work, I'm working on a plan with fallback positions. The attached circuit models as stable with phase margin of 48 degrees (-156dB at 100Hz). If the gate stopper can be smaller then even better. If no gate stopper is required then R11 can be removed and C7 halved (with most of the improvement in PSRR being in high frequencies, e.g. 100kHz goes from -64dB to -96dB).
Another question: the rule of thumb with respect to phase margin is to have at least 45 degrees of phase margin at AolB = 0db. But how strict is the cutoff? Does one die in a ditch over 43 degrees of modeled margin?
If the above proves unstable, I can potentially either replace the MOSFET with a IRLIZ34N and gain more gate stopper head room but also be more constrained on power dissipation or yank out the AD797 and replace it with the turkey TL071 which would seem to have a higher probability of not needing the gate resistor, drop C7 and R11, replace the IPP037N06L3 FET with a IRLI3705N (modeled -132dB at 100Hz with 42 degrees of phase margin hence question above) or pick a FET with weaker performance but proven stability and move on (or use a TL071 and a IRLIZ34N).
PS: now waiting to get hit with more curve balls...
Your suggestion of driving the power supply with a square wave reminds me of the discussion in snaa045a (pg 14 and 15) which is where I got the point I posted in #121.
I knew I would regret not getting the scope model that included a function generator as well. Regarding this, previously you had described a methodology for calculating the inductance of a transformer with a signal generator. I had asked in the context of modelling the in-rush of this power supply. How critical is measuring the inductance of the two transformers I intend to use? Can I get by without doing so? In other words, will I have to bite the bullet on a signal generator anyway and hence I may as well ensure whatever I buy can do square waves.
As I am stubborn, or rather just really want to see if this MOSFET series pass regulator can indeed work, I'm working on a plan with fallback positions. The attached circuit models as stable with phase margin of 48 degrees (-156dB at 100Hz). If the gate stopper can be smaller then even better. If no gate stopper is required then R11 can be removed and C7 halved (with most of the improvement in PSRR being in high frequencies, e.g. 100kHz goes from -64dB to -96dB).
Another question: the rule of thumb with respect to phase margin is to have at least 45 degrees of phase margin at AolB = 0db. But how strict is the cutoff? Does one die in a ditch over 43 degrees of modeled margin?
If the above proves unstable, I can potentially either replace the MOSFET with a IRLIZ34N and gain more gate stopper head room but also be more constrained on power dissipation or yank out the AD797 and replace it with the turkey TL071 which would seem to have a higher probability of not needing the gate resistor, drop C7 and R11, replace the IPP037N06L3 FET with a IRLI3705N (modeled -132dB at 100Hz with 42 degrees of phase margin hence question above) or pick a FET with weaker performance but proven stability and move on (or use a TL071 and a IRLIZ34N).
PS: now waiting to get hit with more curve balls...
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I'm sure. I meant that I have to think about it whereas you can sketch it in a few seconds. I have a lot to learn. Thanks.
If anyone has carried out the hand analysis to derive effective input capacitance of a bootstrapped amplifier, as suggested in (post #132 of this thread), you can compare your results against the LTSPICE plot below.
You'll KNOW you have the right answer if (a) it agrees with the data in this plot; and more importantly (b) you find yourself screaming "Why the hell did you plot it with linear_Y and log_X axes??"
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You'll KNOW you have the right answer if (a) it agrees with the data in this plot; and more importantly (b) you find yourself screaming "Why the hell did you plot it with linear_Y and log_X axes??"
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SGK I recommend that you spend a little time getting familiar with your Output Pole and with your ESR Zero. JackInNJ simulates the Jung Super Regulator using an AD797 and finds (if I interpret his various postings correctly) that it all goes to hell in a handbasket, quickly, if he mis-positions the ESR Zero. I might be mistaken of course.
I recommend that you study the Output Stage (the follower) in vitro; without all the rest of the regulation stuff. Just the follower, the load resistor, and the output capacitors + ESRs. I am sure that clever and creative people are able to imagine many different & innovative ways to perform this study in simulation. Some of their simulation test-benches are no doubt WAY more novel and elegant than mine.
I've attached one circuit example. Its SOLE purpose is to stimulate thinking. I won't provide "technical support" and I won't answer questions about it. If you don't like it, if you don't understand it, if you think it's wrong: just throw it away and use your own ideas. It hasn't cost you any money. I won't answer questions about it and I won't provide "technical support".
I used an Universal Opamp from the LTSPICE library and I gave it a miserably low GBW and an incredibly high Iout_max. The opamp's only purpose is to provide the correct DC bias voltage at the gate of the source follower, which makes the output voltage exactly equal to Vref no matter what load resistor is connected.
Opamp GBW is low because it doesn't need to be high; the opamp only works at DC. The actual input signal comes from "Vstim" at node IN, and the actual signal output is observed at node OUT. Signals don't flow thru the opamp! The opamp's Iout_max is set to a very large number (500mA) so the opamp can, if required, provide the enormous base current needed by low-Beta NPN Bipolar pass transistors if/when you decide to study those.
LTSPICE says that the output pole frequency is around 2-3 kilohertz (moves with load current) and the ESR zero frequency is around 60 kilohertz with the component values given. You can futz with circuit values and move the pole & zero around.
I recommend that you study the Output Stage (the follower) in vitro; without all the rest of the regulation stuff. Just the follower, the load resistor, and the output capacitors + ESRs. I am sure that clever and creative people are able to imagine many different & innovative ways to perform this study in simulation. Some of their simulation test-benches are no doubt WAY more novel and elegant than mine.
I've attached one circuit example. Its SOLE purpose is to stimulate thinking. I won't provide "technical support" and I won't answer questions about it. If you don't like it, if you don't understand it, if you think it's wrong: just throw it away and use your own ideas. It hasn't cost you any money. I won't answer questions about it and I won't provide "technical support".
I used an Universal Opamp from the LTSPICE library and I gave it a miserably low GBW and an incredibly high Iout_max. The opamp's only purpose is to provide the correct DC bias voltage at the gate of the source follower, which makes the output voltage exactly equal to Vref no matter what load resistor is connected.
Opamp GBW is low because it doesn't need to be high; the opamp only works at DC. The actual input signal comes from "Vstim" at node IN, and the actual signal output is observed at node OUT. Signals don't flow thru the opamp! The opamp's Iout_max is set to a very large number (500mA) so the opamp can, if required, provide the enormous base current needed by low-Beta NPN Bipolar pass transistors if/when you decide to study those.
LTSPICE says that the output pole frequency is around 2-3 kilohertz (moves with load current) and the ESR zero frequency is around 60 kilohertz with the component values given. You can futz with circuit values and move the pole & zero around.
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I had started to look at this yesterday. I had noticed that phase margin fell considerably when load was low; voltage gain rolled off more sharply. With your hints re ESR, this morning I found this document very helpful. While relating to LDO regulators with PMOS pass elements, it would seem the points are still relevant.
I haven't yet had the chance to look at your .asc file (I will do so over the weekend) but I did quickly run my stability sim varying the ESR of the output caps while also varying load. See attached. The green and red lines are with 10m Ohm ESR output capacitors with 0.1A and 5A load, respectively. Phase margin with 0.1A load is dangerously close to the 135 degree 'rule of thumb' stability criterion. The blue and turquoise lines change the cap ESR to an arbitrary 100m Ohm. The roll-off in voltage gain versus frequency is less pronounced and hence phase margin is greater. Gain margin contracts however.
I will dig further. I had previously thought that the lower the ESR the better. I see now that's not necessarily the case.
PS: I presume your "output pole" is what the TI paper calls the "load pole".
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(Here's what I mean by "output pole" and "ESR Zero"), a diyAudio post including a link to an article by B. Lee.
Thanks for this. It does indeed highlight the pole and zero position.
I've become more used to looking at the plot of Loop Gain for the entire regulator and find it easier to relate that, obviously, to the paper you linked to (yes, I should have noted it the first time) and the perhaps more easily followed summary TI paper I linked to.
The bit that I don't think is discussed in those papers is the pole added by the gate stopper resistor. Drop a 100 Ohm resistor into your model and observe the significant impact of this pole. Remove it from the full regulator circuit, or lower the amount of resistance, and the output capacitor ESR "compensation" required changes considerably. If I am to fiddle with Rgate on the board (and Ry and Cy which skirt around the op amp) I also need to adjust the output caps accordingly.
Incidentally dropping in a 100 Ohm gate stopper resistor into your circuit would seem to place a pole at c160kHz which matches:
f-3db = 1/(2 x Pi x CISS x Rgate)
SNAA045A.pdf discusses LM4702 driving a Mosfet output stage and states:
An externally hosted image should be here but it was not working when we last tested it.
I need to go over your bootstrapping discussion and graphic from post 132.
(Incidentally, I'm sure you modelled the ESR of the output caps as a resistor intentionally to highlight this parasitic component but of course the same results are achieved by filling in the ESR component in the capacitor profile itself. I add this only to highlight to observers that there is no need to add a bunch of series resistors to capacitors in an LTspice model. Rser can be displayed in the schematic by double-clicking the "Vis" box for that line item.)
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At this stage I'm okay with paying for a larger cap versus delving into yet another circuit. I was thinking that two 10mm diameter 5mm pitch slots for output caps would give me a lot of flexibility. My attraction to the 470uF SEPC caps is merely because I have a bunch of them on my desk. And for no other reason than familiarity I was focused on through hole for the caps.
The attached circuit and board are very much drafts that are work in progress. Nonetheless it would be useful to know earlier rather than later if I am making some major mistakes. Some points as to why I have done certain things the way I have (in no particular order):
- the board will be mounted on the sidewall heat sink of the enclosure
- hence the large heat producing resistors r2-6 have been placed at the top of the board so as to not flow heat directly into the large smoothing caps
- I know I need to place the bypassing caps for the op amp C12 and C13 very close to the op amp
- I need ready access to Cy, Ry and the gate stopper R13
- I have made room for both a SOT23 package voltage reference as well as the larger LM329
- the pre-regulator for Vref is a placeholder for now as I have yet to investigate what this would be for the lower voltage rails
- I thought I may as well implement Kelvin sense
I know this is unfinished and I'm sure I will have to tweak things later anyway. I wanted to try to "break the back of it" this weekend. If I am making "structural" mistakes please let me know.
I was thinking that two 10mm diameter 5mm pitch slots for output caps would give me a lot of flexibility. My attraction to the 470uF SEPC caps is merely because I have a bunch of them on my desk. And for no other reason than familiarity I was focused on through hole for the caps. The attached circuit and board are very much drafts that are work in progress. Nonetheless it would be useful to know earlier rather than later if I am making some major mistakes. Some points as to why I have done certain things the way I have (in no particular order):
- the board will be mounted on the sidewall heat sink of the enclosure
- hence the large heat producing resistors r2-6 have been placed at the top of the board so as to not flow heat directly into the large smoothing caps
- I know I need to place the bypassing caps for the op amp C12 and C13 very close to the op amp
- I need ready access to Cy, Ry and the gate stopper R13
- I have made room for both a SOT23 package voltage reference as well as the larger LM329
- the pre-regulator for Vref is a placeholder for now as I have yet to investigate what this would be for the lower voltage rails
- I thought I may as well implement Kelvin sense
I know this is unfinished and I'm sure I will have to tweak things later anyway. I wanted to try to "break the back of it" this weekend. If I am making "structural" mistakes please let me know.
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I think if you compare the two datasheets, you will find a remarkable similarity between the BC327-40 (thru hole) transistor, and the BC807-40 (SMD) transistor.
(NXP's datasheet) suggests they are the exact same semiconductor die, mounted in two different packages.
(NXP's datasheet) suggests they are the exact same semiconductor die, mounted in two different packages.
Thanks. (I had opened the Fairchild data sheet which didn't show an alternative package from TO-92 and hence had opted to change the component. Mouser UK stock the NXP BC807-40 but not their BC327-40 and hence a search on the latter only revealed the Fairchild and an On Semi end of life component.)
Well I suggest you do as I have done and purchase 500 each of all four part numbers (2 genders x 2 packages) while you still can.
I also bought a lifetime supply of MPS8099, MPS8599, MPS6571, MPS6523, PN4250, BC546, BC556, 2SC3503, and 2SA1381, fearing they will go obsolete very soon.
I bought from Rochester Electronics and Quest Components; but I am in USA and so are they.
I also bought a lifetime supply of MPS8099, MPS8599, MPS6571, MPS6523, PN4250, BC546, BC556, 2SC3503, and 2SA1381, fearing they will go obsolete very soon.
I bought from Rochester Electronics and Quest Components; but I am in USA and so are they.
Filter caps.
As you know I was planning to use brute force large filter caps along with this. The 22,000uF Mundorf M-Lytic AG. Why? Brute force helps, I heard they were very good caps (and don't know any better) and they have low ESR (14m Ohms for the 25V) which I understand is generally a good thing in a power supply. No other sensible reason than those.
I likely have to revisit this choice, at least for the 12V as due to the relatively high Vdropout and catering to a full mains AC spread of 230V -6% +10% I exceed the voltage rating of the caps I was initially looking at (25V). The 40V equivalent have a 35mm rather than 30mm diameter. I can't fit these on a board that's inside the free version of Cadsoft Eagle. So to go to the larger size on the 12V costs a "hobbyist" license for Eagle (c$167 + VAT). Going to the larger size would also mean a board area longer than 10mm which steps me into another cost bucket at SeeedStudio. So hardly economical.
So I can use 10,000uF 40V or 63V Mundorf caps (30mm) for the 12V rail and take the larger pre-reg ripple (it would seem to be about 20mV versus 8mV) or generally take recommendations on other good quality filter capacitors.
Anyone care to make some suggestions? What filter caps do you guys use in your power supplies?
As you know I was planning to use brute force large filter caps along with this. The 22,000uF Mundorf M-Lytic AG. Why? Brute force helps, I heard they were very good caps (and don't know any better) and they have low ESR (14m Ohms for the 25V) which I understand is generally a good thing in a power supply. No other sensible reason than those.
I likely have to revisit this choice, at least for the 12V as due to the relatively high Vdropout and catering to a full mains AC spread of 230V -6% +10% I exceed the voltage rating of the caps I was initially looking at (25V). The 40V equivalent have a 35mm rather than 30mm diameter. I can't fit these on a board that's inside the free version of Cadsoft Eagle. So to go to the larger size on the 12V costs a "hobbyist" license for Eagle (c$167 + VAT). Going to the larger size would also mean a board area longer than 10mm which steps me into another cost bucket at SeeedStudio. So hardly economical.
So I can use 10,000uF 40V or 63V Mundorf caps (30mm) for the 12V rail and take the larger pre-reg ripple (it would seem to be about 20mV versus 8mV) or generally take recommendations on other good quality filter capacitors.
Anyone care to make some suggestions? What filter caps do you guys use in your power supplies?
In my opinion the tricky part will be to synthesize a current source whose current is independent of Vin and whose output impedance is very high. You probably won't want to use a JFET or a current regulator diode because they need more voltage than you're able to provide (Vin - Vbe - Vdegeneration).
So, I suggest you synthesize a constant current by putting a constant voltage across a fixed resistance. This merely requires you to purchase a black epoxy blob (TO-92 or SOT-23 package), just like the other black epoxy blobs on your PCBoard. Solder it down among the resistors and capacitors, just like the other black epoxy blobs. Just another 3 pin active device, no big deal.
HOWEVER some people may consider it blasphemy if they found out that this black epoxy blob contains a voltage regulator IC. Gasp! How dare you use a voltage regulator to build a voltage regulator? (Answer: because it makes good sense, doesn't cost any more money, and gives excellent performance).
So here it is, circuit below. Eleven electronic components, versus 9 components in the 12V version. It provides the low ripple power supply voltage ("V+" in the schematic of post 153 above) for your opamp. It also generates an extremely low ripple Vref voltage for the error amplifier. Input ripple attenuation versus frequency is also attached.
Notice R1 and C1 at far left. They create a pole at 103 Hertz, well below the first zero in the regulator IC's frequency response. This gives excellent ripple attenuation at STAGE1, and subsequent stages make it better and better. You may want to adjust the value of R1 depending on the total current drawn, to minimize the voltage dropped across R1. If so, set R1xC1 greater than or equal to 1.6 milliseconds.
Yikes! I see that I failed to set the final series filtering resistor ("R6") to 3.3K! oops. Making this change will improve attenuation another (3300/75) = 33dB.
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Thanks. I will take a look. I need to get to a footprint/circuit that can work for all 3 voltages (i.e. component substitution allowed but no board changes required) else costs become a bit crazy.
Then I think it's probably a waste of time to design the 12V regulator first. In my opinion, the 3.3V @ 5A regulator is going to be much more difficult to make work. Once you've got a 3.3V, 5 ampere regulator it will be comparatively easy to port it to 12V, but (in my opinion) the other direction is much harder.
It's quite a tight little box you're stuck in. High current AND correct operation at low dropout (Vin-Vout) voltage means you'll either need a darlington BJT pass device or a super duper low threshold (depletion mode) MOSFET. Except you require Rdson << ((Vin-Vout) / 5amperes) and nobody sells depletion mode power MOSFETs with ultra low Rdson. If you try to make the problem go away by providing a large (Vin-Vout) voltage, the pass element will get very hot when conducting 5 amperes.
Pretty much every enhancement mode MOSFET you might use, will need VGS > 2.5V to conduct 5 amperes. That means your min_Vinput is 5.8 volts and your max_Vinput is bigger still. Lotta power getting dissipated in the worst case. Darlington BJT's comparable "VGS" is nearly a factor of two lower at room temperature, and more than a factor of two lower at heatsink temperature. Hmmm?
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