Power Supply Resevoir Size

[OnAudio]

Originally Posted by gootee

Here's a zoomed-in view of the first drum strike, at about 9.7 seconds.

This is with only 1600 uF or reservoir capacitance per rail.

Cheers,

Tom

Is that an amplified inverted copy of the drum kick on positive rail ?

[gootee]

Here's a better zoomed view of the 3x 10000 uF caps' currents precisely tracking the load's output signal voltage.

They don't get to take a breath until the next charging pulse...

Cheers,

Tom

[gootee]

Originally Posted by OnAudio

Is that an amplified inverted copy of the drum kick on positive rail ?

See the post after yours (i.e. post 372).

It shows that it's exactly as I've been saying all along:

The rail CURRENTS _ARE_ the signal, non-inverted, and they come from the capacitors.

Each rail does one polarity. So the currents look like a push-pull version of the signal.

The rail VOLTAGE just sags a little when the transistors open up, to let just the right amount of current out of the caps to create the load voltage.

Edit: It looks like the current for the negative rail cap (fC5) somehow got inverted, in the first image in post 370 (the 1600 uF version of the zoomed drum strike).

Cheers,

Tom

[Terry Given]

Hi Tom,

yeah I think that proves it quite conclusively. theory + measurement + simulation are in complete agreement. its almost as if "Current Flows In Loops - Minimise Them" ought to be a mantra.....

cheers
Terry

[MagicBox]

Originally Posted by gootee

Here's a better zoomed view of the 3x 10000 uF caps' currents precisely tracking the load's output signal voltage.

They don't get to take a breath until the next charging pulse...

Cheers,

Tom

That's an ickey distortion right there in the middle! At the back slope of the second soundwave peak, when the caps at the 'zereocrossing' of the signal are in transit between exclusive supplying and simultanious supplying and charging. You see some overshoot when the caps 'drop' in that transition area, affecting the output (note the small vertical drop exactly at the point in time where the cap is supplying and starts being loaded while the negative rail cap starts providing the current.

This is actually a very intriguing aspect. Zerocrossing distorting effects seem to be introduced by caps 'alternating' between each other in supplying load. This could either be induced by the output stage crossover, or be an additional source of crossover inherent to symmetrical supply output.

All in all awesome work here in this thread!

[gootee]

Originally Posted by fas42

Just a quick comment for now, Tom ... what that highlights, apart from nasty looking voltage rails(!!), is the apparent tradeoff between maintaining voltage headroom and the load drain modulating the voltage: with the 30,000uF the spikeness is much reduced but the caps are steadily being drained, from 71V to about 66V, the rectifier pulse of current is insufficient to top up the charge, at some point a balance will be reached, but what voltage will that be? Then, at the other end of behaviour, the minimal 1600uF produces terrible glitches of voltage drops, to 45-50V, but then recharges very quickly because of the lower capacity, so the headroom voltage overall remains close to 71V.

So which way is better, and what are the other "solutions" ...?

Frank

Frank,

Good insight. That is the trade-space that needs to be quantified.

The voltage goes back up, a few seconds after that sim ends, by the way. But that points out a possible criterion for choosing the reservoir capacitance: They have to be large-enough to have enough charge to supply a sustained "short term" demand, i.e. at least until the next charging pulse, but also need to be small-enough that a) they don't drag the voltage too low for a worst-case burst between charging pulses, and b) they aren't so large that they can blast out a LOT more current than a charging pulse can supply, because then, if they're unlucky with the size and timing of the demand versus the size and timing of the charging pulses, they could just continue to force the rail voltage lower and lower. That's part of the equation we need!

This looks like a probability problem, too. What fun! (groan).

ESR and ESL play a role there, too, both those of the capacitors and those of the interconnects on both sides of them. And the transformer and rectifiers will probably need to be able to supply extra-big charging pulses, sometimes.

Cheers,

Tom (going to bed now)

[gootee]

Originally Posted by Terry Given

Hi Tom,

yeah I think that proves it quite conclusively. theory + measurement + simulation are in complete agreement. its almost as if "Current Flows In Loops - Minimise Them" ought to be a mantra.....

cheers
Terry

It's a beautiful thing, yes?!

Love that mantra.

(And I still haven't even gotten to the decoupling caps, yet!)

[gootee]

By the way, the plotted error (bottom plot pane in post 370's two plots, for example) appears to be meaningless, so far, since it varies only very slightly due to capacitor effects. It looks like I need to just devise an "ideal" amplifier, using spice's controlled sources, or something, so that the amplifier errors can be completely eliminated. That way, the error (difference between output and input) could give a valuable representation of any changes in the inaccuracies of the reproduction, due to changes made in the power supply or distribution, and should be able to be used to pinpoint their sources and might lead us to patterns or rules (or equations :-) that we can actually use.

I will probably also repeat the plots I did today, but with extremes of capacitance, both large and small, to possibly shd more light on the trends and tradeoffs that were noted.

Now I really am going to bed...!

Cheers,

Tom

[Terry Given]

I have to agree with MagicBox - awesome thread.

Tom - you guys have done all the hard work, a mantra was the least I could do.

the droop is probably due to the transformer leakage inductance. it (assuming its the same as the one a few pages back) is 2%, but the crest factor is quite high so the ~ 6% droop will be this (only needs CF = 3, quite reasonable).

it wouldnt be hard to prove. extracting the leakage inductances from the transformer model would also make it easy to play with.

It would be interesting to see what the leakage inductance is for non-toroidal transformers - without interleaving I would expect it to be 5-10% so these would have far more droop.

PFC Boost converters would work nicely here - placed at the amplifier they would have very little output capacitance and draw nice sinusoidal input current. hell, it wouldnt be hard to make them compensate for the nonlinear transformer magnetising current, and draw unity power factor low-thd sinusoidal mains current. which must sound better, right? oops, crossed the fine line between the sublime and the ridiculous.

so turning it around, for a given transformer (ie leakage inductance) the allowable droop (before clipping sets in) sets an upper limit on the DC bus capacitance. somehow I dont think that will prove to be a useful design rule. ah well....

ISTR doing some maths a while ago to figure out conduction angle, crest factor and thd given load, cap & leakage inductance. I'll try and find it.....

[Nico Ras]

Tom & Fred, I think between the two of you we are going to conclude that there is a definite rule of thumb and that just throwing money away to add as much capacitance as you can afford is not a solution. I think this is going to be an eye opener for most audio designers and possible a reference thread to any future designs.