Thanks John!
I will build it up on a new RB module to test your recommendations.
Cheers,
Oliver
& Put the decoupling caps tight to the 1541a pins and I'll buy it
Hi dvb-project,
Yes that should work.
BCK needs to be around 800mVpp (approx. 1.2V DC bias) without using an attenuator, so this problem has to be solved in the BCK divider circuit.
BCK overshoot (on the scope) is usually caused by an incorrect probe. One needs to use HF probes, something like this:
3GHz RF Probe
Scope bandwidth also has to be large enough, 100 MHz bandwidth would be acceptable.
I also suggest to "measure" with your ears after checking the signal with the scope. What looks good on the scope can still sound lousy
Yes that should work.
BCK needs to be around 800mVpp (approx. 1.2V DC bias) without using an attenuator, so this problem has to be solved in the BCK divider circuit.
BCK overshoot (on the scope) is usually caused by an incorrect probe. One needs to use HF probes, something like this:
3GHz RF Probe
Scope bandwidth also has to be large enough, 100 MHz bandwidth would be acceptable.
I also suggest to "measure" with your ears after checking the signal with the scope. What looks good on the scope can still sound lousy
BCK is extremely critical, attenuators are best avoided here, even plain series resistors are a problem (noise). Best results can be achieved by using 800mVpp BCK signal (not derived from an attenuator) with less than approx. 300 Femto seconds of jitter, but this is kind of "problematic"
So simply remove the BCK attenuator and hope for the best:
- Remove 68R, 220R, 10mH choke and all 100 Ohm resistors. Feed source BCK signal directly to pin 2.
In the upper post you recommed to cancel the BCK 5x100R att. and the complete divider circuit parts for the 1.2V bias.
Without all parts i have the full BCK output voltage from Ian´s FIFO at PIN 2 and no Bias...?
I think i have not really understood what to do...
He does like his SD player! Good to have such clients.
Interesting stuff: he also mentions to prefer TDA1543 over 1541 because it [might be] internally less jitter prone and without external jitter (like in Johns implementations) the DEM logic of the 1541 has no advantage. . .
Even though he boasts a non-tech site, it does sound techy . . .
I attached the BCK output signal from Ian´s FIFO.
Attachments
Hi dvb-project,
Resistive attenuators lead to less steep transients, this opens the door for trigger uncertainty in noisy environments.
That's why I suggested to directly connect FIFO BCK out to pin2. This is the best compromise given the practical drive circuit limitations.
I also suggest to use shortest possible connection between FIFO circuit and TDA1541A BCK input. With shortest possible I don't mean a few centimeters mut more like a few millimeters.
If you want to experiment with a BCK attenuator you could try a similar diode attenuator like with WS and DATA. The pull-up resistor value then has to be lowered to 120 Ohms. The resistor value needs to be as low as possible, but it's minimum value is limited by the typical 25mA max. output current of the FIFO reclocker.
Resistive attenuators lead to less steep transients, this opens the door for trigger uncertainty in noisy environments.
That's why I suggested to directly connect FIFO BCK out to pin2. This is the best compromise given the practical drive circuit limitations.
I also suggest to use shortest possible connection between FIFO circuit and TDA1541A BCK input. With shortest possible I don't mean a few centimeters mut more like a few millimeters.
If you want to experiment with a BCK attenuator you could try a similar diode attenuator like with WS and DATA. The pull-up resistor value then has to be lowered to 120 Ohms. The resistor value needs to be as low as possible, but it's minimum value is limited by the typical 25mA max. output current of the FIFO reclocker.
Hi triode_al,
If only I could simply share perceived sound quality of various prototypes. But even modern technology fails to offer this possibility over the internet.
So I try to use a visual example instead, attempting to show the audible differences using pictures.
How DAC chips sound relies heavily on time resolution that can be obtained with the application.
I attached a photograph to illustrate this. Both pitctures have the same vertical resolution (150 pixels). The one on the left has only 20 pixels horizontal resolution, the one on the right 200.
The horizontal resolution -could- be compared with time resolution, the vertical with bit resolution.
If we use both, a DAC chip that offers low jitter contribution and an external clock circuits offering extreme low jitter we could end up with the picture on the right.
Use your own imagination for the impact this would have on perceived sound quality.
But what has the TDA1543 got to do with this ?
The TDA1543 is based on quiet current mode logic with 400mV signal swing and constant load current. The on-chip circuit is as simple and basic as it gets. This leads to very low DAC chip jitter contribution and that is exactly what we need to achieve highest possible time resolution.
TDA1541A is based on current mode logic too, but the on-chip circuits are more complex (DEM circuit), so DAC chip jitter contribution is likely to be higher. The advantage of the DEM logic is increased bit accuracy without (LASER) trimming, but without matching time resolution (that is degraded by this same DEM circuit), the DEM circuit has little added value.
These DAC chip properties only start to have a big impact when external circuits are approaching perfection (extreme low jitter, extreme high time resolution). With conventional applications with low time resolution it has no advantages to use a TDA1543.
Simply using a DAC chip with higher bit accuracy results in the third picture (1000 pixels vertical resolution instead of 150 pixels) but with same low horizontal (time) resolution of 20 pixels. It is difficult to see any differences between this third picture and the left photograph in the first picture. Differences are there but rather subtle.
In a photograph we can simply increase horizontal resolution. In the time domain this is a whole different story. Increasing sample rate and clock frequencies, and using noisy CMOS logic does not lead to higher time resolution in practical circuits, often the opposite is achieved.
If only I could simply share perceived sound quality of various prototypes. But even modern technology fails to offer this possibility over the internet.
So I try to use a visual example instead, attempting to show the audible differences using pictures.
How DAC chips sound relies heavily on time resolution that can be obtained with the application.
I attached a photograph to illustrate this. Both pitctures have the same vertical resolution (150 pixels). The one on the left has only 20 pixels horizontal resolution, the one on the right 200.
The horizontal resolution -could- be compared with time resolution, the vertical with bit resolution.
If we use both, a DAC chip that offers low jitter contribution and an external clock circuits offering extreme low jitter we could end up with the picture on the right.
Use your own imagination for the impact this would have on perceived sound quality.
But what has the TDA1543 got to do with this ?
The TDA1543 is based on quiet current mode logic with 400mV signal swing and constant load current. The on-chip circuit is as simple and basic as it gets. This leads to very low DAC chip jitter contribution and that is exactly what we need to achieve highest possible time resolution.
TDA1541A is based on current mode logic too, but the on-chip circuits are more complex (DEM circuit), so DAC chip jitter contribution is likely to be higher. The advantage of the DEM logic is increased bit accuracy without (LASER) trimming, but without matching time resolution (that is degraded by this same DEM circuit), the DEM circuit has little added value.
These DAC chip properties only start to have a big impact when external circuits are approaching perfection (extreme low jitter, extreme high time resolution). With conventional applications with low time resolution it has no advantages to use a TDA1543.
Simply using a DAC chip with higher bit accuracy results in the third picture (1000 pixels vertical resolution instead of 150 pixels) but with same low horizontal (time) resolution of 20 pixels. It is difficult to see any differences between this third picture and the left photograph in the first picture. Differences are there but rather subtle.
In a photograph we can simply increase horizontal resolution. In the time domain this is a whole different story. Increasing sample rate and clock frequencies, and using noisy CMOS logic does not lead to higher time resolution in practical circuits, often the opposite is achieved.
Attachments
Hi Eldam,
The I/V stage for both TDA1541A and TDA1543 have similar complexity. Both -must- fully meet TDA1541A and TDA1543 50mVpp output compliance. DAC chip output signal bandwidth also needs to be limited prior to I/V conversion.
I achieved highest time resolution with the TDA1543 using novel circuits that were designed at the end of 2012. This would then translate to the picture on the right.
I use one of the cleanest digital audio sources available today (SD-transport). I use a novel electronic tuning fork that replaces the relatively noisy and jittery crystal oscillator. Fastest available ECL circuit was used for BCK divider.
I attached a picture of the SDV1-player prototype during construction.
It contains the final SD-player module and a binary stepped shunt volume control.
The integration of SD-player and volume control eliminates two RCA interlinks and enables one local star ground. The degrading of a single RCA interlink is quite alarming at these extreme performance levels. Biggest problem are the multiple metals in the connectors. These will reduce resolution, a single contact can already mask a few LSBs. In the SDV1-player I soldered OFC litz wire directly to both PCBs using solder containing 3% silver.
In order to maintain maximum resolution in the power amp, I developed new Circlotron monoblocks (pictures). These have a differential input stage based on matched medium power lateral MOSFETs running on a separate, very clean high voltage supply (100 … 200V). The Circlotron output stage contains two closely matched lateral power MOSFETs. So there are total of 4 lateral MOSFETs used in the complete power amplifier. rated output power of this version is around 30 watts rms in 8 Ohms.
Logical consequence is integrating the monoblocks with the SDV1-player. This eliminates the last two RCA interlinks and enables a local star ground for all circuits. I attached some pictures of the experimental ISD-player prototype during construction.
The I/V stage for both TDA1541A and TDA1543 have similar complexity. Both -must- fully meet TDA1541A and TDA1543 50mVpp output compliance. DAC chip output signal bandwidth also needs to be limited prior to I/V conversion.
I achieved highest time resolution with the TDA1543 using novel circuits that were designed at the end of 2012. This would then translate to the picture on the right.
I use one of the cleanest digital audio sources available today (SD-transport). I use a novel electronic tuning fork that replaces the relatively noisy and jittery crystal oscillator. Fastest available ECL circuit was used for BCK divider.
I attached a picture of the SDV1-player prototype during construction.
It contains the final SD-player module and a binary stepped shunt volume control.
The integration of SD-player and volume control eliminates two RCA interlinks and enables one local star ground. The degrading of a single RCA interlink is quite alarming at these extreme performance levels. Biggest problem are the multiple metals in the connectors. These will reduce resolution, a single contact can already mask a few LSBs. In the SDV1-player I soldered OFC litz wire directly to both PCBs using solder containing 3% silver.
In order to maintain maximum resolution in the power amp, I developed new Circlotron monoblocks (pictures). These have a differential input stage based on matched medium power lateral MOSFETs running on a separate, very clean high voltage supply (100 … 200V). The Circlotron output stage contains two closely matched lateral power MOSFETs. So there are total of 4 lateral MOSFETs used in the complete power amplifier. rated output power of this version is around 30 watts rms in 8 Ohms.
Logical consequence is integrating the monoblocks with the SDV1-player. This eliminates the last two RCA interlinks and enables a local star ground for all circuits. I attached some pictures of the experimental ISD-player prototype during construction.
Attachments
Hi, John,
I'm uncertain as to what is your latest I/V circuit. The last one I recall seeing was based on single grounded gate FET with a resistor drain load. Your comment above leads me to wonder whether you might now be using some more complex design. Could you confirm exactly what I/V circuit you now use? Thanks.
Hi dear -EC-,
I am glad that you are close to production/marketing stage (at last) ...
I hope that you will also be offering some prototypes for sale.
You must be aware that the heatsinks are not very aerodinamic and will limit the unit's max speed
Are those Panasonic FM caps? Good caps, but I am partial to Rubycon ZL wich produces best bass (even with passive I/V) and overall sound.
Having solved the SD card problems I had before (was my laptop that did the mess) I can declare that the SD player (I use a competing brand for the moment) integrated to a M1 DAC offers the best option to aproach nirvana of sound source.
Maybe in the future a player with a big solid-state "drive" could be created, with intermitent connection to PC for feeding files...
I will now upgrade my DI4M scrambler/interpolator DAC which I love.
About attenuators, as I am a primitive kind of DIYer, I use variable resistors with the lowest temperature coefficient I can find and then trim (multiturn is better) them until it works.
Thank you for all the fun and good luck,
M.
I am glad that you are close to production/marketing stage (at last) ...
I hope that you will also be offering some prototypes for sale.
You must be aware that the heatsinks are not very aerodinamic and will limit the unit's max speed
Are those Panasonic FM caps? Good caps, but I am partial to Rubycon ZL wich produces best bass (even with passive I/V) and overall sound.
Having solved the SD card problems I had before (was my laptop that did the mess) I can declare that the SD player (I use a competing brand for the moment) integrated to a M1 DAC offers the best option to aproach nirvana of sound source.
Maybe in the future a player with a big solid-state "drive" could be created, with intermitent connection to PC for feeding files...
I will now upgrade my DI4M scrambler/interpolator DAC
which I love.About attenuators, as I am a primitive kind of DIYer, I use variable resistors with the lowest temperature coefficient I can find and then trim (multiturn is better) them until it works.
Thank you for all the fun and good luck,
M.
Not all the crystal oscillators are jittery and noisy, depends on the crystal quality. Good crystals are expensive, while mostly of the commercial designs use poor crystals, Finally, the only problem is the budget.
The OCXO showed in the attached image has a phase noise better than -130dBc@10Hz, more than needed in digital to analog converters.
The crystal showed has an ESR of less than 10 ohm and Q greater than 150K, that means it can easily reach at least -120dBc@10Hz with a 2 transistors Butler or a Driscoll oscillator. This is a cold welded package polished AT crystal. Obviously it costs much more than the poor crystals used in commercial XO, but it's cheaper than the SC-cut crystal used in the above OCXO.
Also, I believe the better way is to don't use any divider for the BCK, feeding it directly from the XO, If the source need higher clock frequency than the BCK, IMHO, better use a frequency multiplier for that, rather than divide the MCLK for the BCK.
Attachments
Hi John,
Thanks.
I thought that the TDA 1543 was simplier to make sing after reading your evolutions. I have been ending to make your TDA1543 DC-coupled output stage & passive i/v for a CD player. After I will begin your DAC with the 1541 but in a DIY way (veroboard...). I try to have a simple but good enough design for the clok because I want to reclock a squeezebox receiver in the same time but without spend to much money for a bader result (length of wire, no experience or knowledge with buffer!). Contributors gave me many tips these days about clocks like ANdrea Mori did... that's what I need to close this project which is very interesting.
As I read Squeezebox receiver is very good with 1.8 V clock input, I will try this value and not the 0.8 you advise for the BCK input of the tda1541 with clock divider and the 180R serie (or signal diode) in the last public design you gave(but I will try at last the signal diode: 2 BAT17 = 1V down ?).
Elegant box, I like the use of wood. It looks a little like the pretty Sphinx product.
Hi Max Lorenz,
The Rubycon ZL : i had good result with them sometimes, The FM can be good, did you try Nichicon Muse Z serie for the powersupply of outputsage ? With or without a 100 nf MKT (the blue one of philips or sometimes the green ones of Vishay) they work better than the rubycon or Panasonic than I have to use before an OSCON in a digital stage. Try too the Muse Z serie with a 100 nf (or more) MKP 400V... ok long legs but try...I try sometimes with 100 nf polystyren (Multicap) or russian teflon.
Thanks.
I thought that the TDA 1543 was simplier to make sing after reading your evolutions. I have been ending to make your TDA1543 DC-coupled output stage & passive i/v for a CD player. After I will begin your DAC with the 1541 but in a DIY way (veroboard...). I try to have a simple but good enough design for the clok because I want to reclock a squeezebox receiver in the same time but without spend to much money for a bader result (length of wire, no experience or knowledge with buffer!). Contributors gave me many tips these days about clocks like ANdrea Mori did... that's what I need to close this project which is very interesting.
As I read Squeezebox receiver is very good with 1.8 V clock input, I will try this value and not the 0.8 you advise for the BCK input of the tda1541 with clock divider and the 180R serie (or signal diode) in the last public design you gave(but I will try at last the signal diode: 2 BAT17 = 1V down ?).
Elegant box, I like the use of wood. It looks a little like the pretty Sphinx product.
Hi Max Lorenz,
The Rubycon ZL : i had good result with them sometimes, The FM can be good, did you try Nichicon Muse Z serie for the powersupply of outputsage ? With or without a 100 nf MKT (the blue one of philips or sometimes the green ones of Vishay) they work better than the rubycon or Panasonic than I have to use before an OSCON in a digital stage. Try too the Muse Z serie with a 100 nf (or more) MKP 400V... ok long legs but try...I try sometimes with 100 nf polystyren (Multicap) or russian teflon.
What about going balanced output using 2 TDA1543 (feed,ing one with inverted data) then a balanced L pad stepped attenuator then directly to the balanced Circlotron (if possible increase the I/V output to avoid the drivers in the Circlotron, leave only the lateral mostefs)
Nice find! May I ask what the price of these babies is? Also, is it spec'ed at -130db or did you measure? I can't find the datasheet on the Laptech page (don't know which one it is....
As long as BCK is reclocked, it's probably indeed better to feed the cleanest clock signal to the reclocker and the multiplied clock signal to the source. The picture you show is of a 11mhz crystal though