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Old 9th July 2006, 04:24 PM   #531
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Just FYI a similar idea for a DAC at APL in the States, involving a massive parallel array of AKM DAC chips & a 6H30 output stage.

http://www.aplhifi.com/phpBB/viewtopic.php?t=431

Dave
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Old 9th July 2006, 04:54 PM   #532
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Default USB and jitter

Hi MGH,

Thanks for your tip [post#529]

Yes as this article indicates, jitter problems can be expected from USB. Just like I already noted [post#500].

Back to the CS8412 connected close to the transport, it has jitter on BCK, I reclocked BCK, DATA and WS with the 16MHz master clock from the transport (using 2 cascaded D-flipflop for each signal) This works perfectly, when triggering the oscilloscope on the masterclock (reference), the reclocked BCK is rock solid, BCK from the CS8412 already shows jitter. So this way very low jitter I2S signals can be dereived from a jittery SPDIF interface on the transport side.

Now let's tackle the USB interface, the PCM2706 generates the jittery I2S signals just like the CS8412 did in the transport. So all that is needed is reclocking it with the "USB masterclock". To be on the safe side, a cheap USB interface add-on card is used. I got one right here from Lacie, it uses a 48MHz crystal to clock the USB host controller chip (D720101J from NEC). So we are going to do a clock mod on this card, the crystal oscillator module from this card is removed and connected to a clean 5V supply, the output signal (48MHz) is fed back to the D720101J. It is also used to drive the D-flipflops to reclock the I2S signals from the PCM2706, the USB interface can be placed very close to this USB card. Now we have a I2S low jitter signal from the USB bus.

Now for the proof, reclocking can actually work, I added some oscillograms to show the effect of reclocking, I created a worst case situation with an abundance of jitter, to show it also works in extreme situations. The signals can be reclocked synchronously in this particular setup because both SPDIF and masterclock run in sync,(SPDIF signal is generated using the master clock).

Oscillogram top left: upper trace, master clock (16MC) from the mini clock upgrade, lower trace the jittery BCK. Oscilloscope is triggered on the master clock.

Oscillogram top right: Upper trace, same master clock, lower trace BCK after reclocking, spot the difference with the previous oscillogram.

Oscillogram bottom left, the oscilloscope is now EXTERNALLY triggered by the master clock, upper trace, you guessed, the reclocked BCK, lower trace, no comment needed.

Oscillogram bottom right, same signals but zoomed in using the X10 setting, still triggering externally to the master clock. In a more practical situation jitter is far less, more in the region of 300...600pS. Now a low jitter master clock is needed to further reduce jitter. To obtain very low jitter values, circuitry layout becomes very important. It's also good practice to separate both data and synchronization signals (separate chips) to avoid crosstalk were possible.

Clearly noticable is the phase shift of the reclocked BCK signal with the jittery one, this could cause sync problems, so both DATA and WS are reclocked the same way to restore phase relation, not because there were some unused D-flipflops left.
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Old 9th July 2006, 05:41 PM   #533
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John: petje af hoor!

These oscillograms shows enought to answer my question. Triggering does the trick to show (the absense) of jitter. Very nice!
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Old 9th July 2006, 05:45 PM   #534
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Default Re: Non linear interpolation

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Originally posted by -ecdesigns-
Read [post#151] very carefully, it already proves that I tried similar setups, but sound quality degraded, since the time interval between samples has to remain constant.
I’m curious; did you try every combination of 8 DACs on 64 shift register taps? There are millions of permutations. Although most random distributions of 8 or 16 DACs on 64 taps are worse than the linear one, there are a few that are very much better. I doubt you “accidentally” tried one of those before reaching your conclusion.
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Old 9th July 2006, 06:55 PM   #535
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Default Changing taps

Hi Ulas,

Thanks for your reply [post#534]

No I didn't have time to try them all, since I am not retired yet . When placing taps at irregular intervals, like 0,12,24,35,45,53,59,63 the distance between each interpolated sample differs. If the time between each subsample is not the same (I used 8BCK multiples in the octal D-I DAC), you end up with a periodically varying virtual sample rate (FM modulation). Another problem is adding ripple, caused by shaping individual steps. The average virtual sample rate is also lowered, this could increase interference.

So you either use the same time between samples or you don't. Using the same time between samples is already used in the octal D-I DAC. But perhaps I missed something.

Could you explain how you connected the tabs? and why?
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Old 9th July 2006, 08:55 PM   #536
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Quote:
When placing taps at irregular intervals, like 0,12,24,35,45,53,59,63 the distance between each interpolated sample differs.
On this way Ulas wants to try to keep up with the jitter produced in his own setup used.

(sorry for the readers of this above mentioned comment from me, and possible don't know the background of it, but others who know, they understand this post completely.)
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Old 9th July 2006, 09:49 PM   #537
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Quote:
Originally posted by tubee


On this way Ulas wants to try to keep up with the jitter produced in his own setup used.

(sorry for the readers of this above mentioned comment from me, and possible don't know the background of it, but others who know, they understand this post completely.)

Do you really think the above post makes more sense knowing the background ?
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Old 9th July 2006, 10:05 PM   #538
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Default Re: Split the clock signal ?!!!!!?

Quote:
Originally posted by NjoyTHEMUSIC
Hi John (ecdesigns) -
Hijack ? Are you calling me 'Robin Hood' ?!?!
Dennis Moore, perhaps?

Quote:

BUT- Will feeding/splitting the output clock signal from the Trichord module between the transport servo pcb and HD100 IC have any delerious effect on the integrity of the clock signal ?
You have little choice. As things stand the clock is connected in one of two ways. The first is to the servo/decoder and then on to the PMD100 via an onboard buffered output on the main decoder chip. Before he was captured and bannished, Anticitizen One was very vocal in his disapproval of this technique.
The second sends the clock directly to the servo/decoder and the PMD100, the option I'd recommend. The Trichord should be more than capable of driving two inputs.
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Old 10th July 2006, 09:27 AM   #539
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John,
That is such a good physical example of jitter.
You really can imagine the hell it would play upon your desired signal.

Cheers,
Phil
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Old 10th July 2006, 12:21 PM   #540
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Default Re: Split the clock signal ?!!!!!?

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Originally posted by rfbrw



The second sends the clock directly to the servo/decoder and the PMD100, the option I'd recommend. The Trichord should be more than capable of driving two inputs.

Hi rfbrw ! - Thanks for the reply ...

I was hoping this was going to be the case !!! I just wanted to check, before I started hacking up the data cable in the Copland (!)
I'll make the modification (fingers crossed).

Also - I've noticed that the ac power cables that feed the servo pcb
are routed directly under the dac/analogue pcb - So, I've now used some shielded multicore cable (shield grounded) and re-routed it along the top/rear of the casework so it's nowhere near any ccts, other than where it inserts into it's designated connection point.


Thanks again ...
-Andy-
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