@ andrea_mori
Can you please answer these questions first:
1. Why can't you see the 590.4ps time domain random jitter and deterministic jitter in your phase domain measurement?
2. Why you see a RMS 7.68ps (with including the noise floor) time jitter RMS 66.19ps in phase domain ?
2. The huge difference in time jitter before and after FifoPi can be directly seen from the analog waveforms, why we can not find the difference in your phase noise plot.
Regards,
Ian
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I would repeat the request of Ian.
There is an elephant in the room here.
There is an enormous gain in quality in the screenshots before/ after, provided by Ian.
I am sorry to say, but these are rather coincident with my perception of reality.
Just and simply reclocking a brutally dirty clock like that of an RPi should bring a result like this.
So it would be very much appropriate, properly in this thread, to clear up this discrepancy in the measurement of Andrea.
And please don't refer to other factors, nobody is claiming problems with the TimePod itself, we do know and follow John since more than 10 years.
The tool is ok, the responsability is on the experimenter.
My feeling is that Andrea is so much concentrated on those particular problems of close in noise floor modulations, that he is neglecting, overlooking the greater picture.
And this is a problem because resulting in him suggesting that the original RPi clock would look better when it is ~1000 times more jitter infected than the output of the Fifopi...
At this point I am getting curious about that DDS generator, how dirty it is in reality?!
And please stop to be the victim, Andrea. I do not have any stake neither with Ian nor with You.
But I feel a distortion of reality here, and do not like that.
And this all only refers to the Fifopi measurements.
Your job on the oscillators is truely great, me myself will line up in the queue, the measurements (and the design) are exceptional quality.
Ciao, George
There is an elephant in the room here.
There is an enormous gain in quality in the screenshots before/ after, provided by Ian.
I am sorry to say, but these are rather coincident with my perception of reality.
Just and simply reclocking a brutally dirty clock like that of an RPi should bring a result like this.
So it would be very much appropriate, properly in this thread, to clear up this discrepancy in the measurement of Andrea.
And please don't refer to other factors, nobody is claiming problems with the TimePod itself, we do know and follow John since more than 10 years.
The tool is ok, the responsability is on the experimenter.
My feeling is that Andrea is so much concentrated on those particular problems of close in noise floor modulations, that he is neglecting, overlooking the greater picture.
And this is a problem because resulting in him suggesting that the original RPi clock would look better when it is ~1000 times more jitter infected than the output of the Fifopi...
At this point I am getting curious about that DDS generator, how dirty it is in reality?!
And please stop to be the victim, Andrea. I do not have any stake neither with Ian nor with You.
But I feel a distortion of reality here, and do not like that.
And this all only refers to the Fifopi measurements.
Your job on the oscillators is truely great, me myself will line up in the queue, the measurements (and the design) are exceptional quality.
Ciao, George
1.
I don't see any jitter, I measure the phase noise, I have calculate the jitter using a converter.
As I said several time I don't care about jitter since it's a standalone number without the noise spectrum, useless for me.
You continue arguing about LRCK, but the phase noise plot tells that you have even higher noise floor in the SCK.
For your convenience, forgive for a while the LRCK since you don't trust the measurement with the Timepod at low frequency, but you have the identical noise floor issue at a frequency (12.288 MHz) where the reliability of the Timepod is indisputable.
Can you explain the reason?
2.
Because if you change the integrating bandwidth the jitter change too.
As you can see it's an arbitrary value, while the phase noise plot is absolute, it shows exactly the noise in dB of all the sideband.
You can't argue an absolute value, while you can argue an arbitary value.
3.
Because the noise floor of the output is very high, I suspect it's due to the crosstalk.
Why this crosstalk?
Are you using the PLL of the FPGA?
Have you took a look at the waveform before the D-FF?
I don't see any jitter, I measure the phase noise, I have calculate the jitter using a converter.
As I said several time I don't care about jitter since it's a standalone number without the noise spectrum, useless for me.
You continue arguing about LRCK, but the phase noise plot tells that you have even higher noise floor in the SCK.
For your convenience, forgive for a while the LRCK since you don't trust the measurement with the Timepod at low frequency, but you have the identical noise floor issue at a frequency (12.288 MHz) where the reliability of the Timepod is indisputable.
Can you explain the reason?
2.
Because if you change the integrating bandwidth the jitter change too.
As you can see it's an arbitrary value, while the phase noise plot is absolute, it shows exactly the noise in dB of all the sideband.
You can't argue an absolute value, while you can argue an arbitary value.
3.
Because the noise floor of the output is very high, I suspect it's due to the crosstalk.
Why this crosstalk?
Are you using the PLL of the FPGA?
Have you took a look at the waveform before the D-FF?
In the same time:
If Andrea would have put in this way:
Look, Ian, it is true that the effect of your board is doing this and this (and showing the effect of cleanup >50dB) - - but look, after that, here in the close in noise floor modulation we still see these kind of residual problems...
Than I would be fully with You, Andrea, and I would suggest to Ian to take into account the results of an instrument with much better, lower background..
Ciao, George
If Andrea would have put in this way:
Look, Ian, it is true that the effect of your board is doing this and this (and showing the effect of cleanup >50dB) - - but look, after that, here in the close in noise floor modulation we still see these kind of residual problems...
Than I would be fully with You, Andrea, and I would suggest to Ian to take into account the results of an instrument with much better, lower background..
Ciao, George
FWIW, I run FIFOpi with no clocks installed (Andrea clock self powered). I found to my ear an improvement in sound by adding cap directly to VIN pins of NB3L533-D (BG NX HI-Q). I presume that PS impacts noise on buffer chip but I have no ability to measure.
Please, take a look at the BCK phase noise plot above 100 Hz, not the close in noise.
What do you see?
The FifoPi output is 10 to 15 dB better than the RPI out, but the MCK is 20 to 25 dB better.
Why?
It looks like I have interest to discredit Ian's FIFO buffer, but I have bought 4-5 boards from Ian and I have used one of them in a high-end system that sounds very good.
But until I replaced the clock of the source it did not sound so good.
Why?
BTW, I'm here to help the community if I can, so I have some suggestion for the designer, although he is free to ignore my indications:
- use optical based isolator rather than RF based type
- use separate ground for the isolators
- don't mix all the output signals inside the same reclocker IC, use distinct flip-flop like the LVC1G374
- don't use anyway the PLL of the FPGA
- in a future release think seriously to change the whole architecture, generating the clock signals outside the FPGA, making the FPGA slaved to the DAC
You are free to trust or not the reliability of the measurements, I have done the job for the audio community not for me.
Our target is a little different from the FifoPi.
I hope JohnW will repeat the measurements, as I said I look forward to see his results.
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I don't know about everyone else here, but its not clear to me what DPLL frequency shifting should look like on a phase noise plot. Seems like it would depend on some idea of what frequencies the DPLL is jumping between and the periodicity or lack thereof with which the small jumps occur. If we don't have a model for that, how could one estimate what it should look like on a phase noise plot? Which frequency would be deemed the carrier, any of them?
At least to me, it doesn't seem like it operates as a a fixed frequency clock in the same sense that good crystal oscillator clocks do. Possibly not what TimePod is really designed for?
At least to me, it doesn't seem like it operates as a a fixed frequency clock in the same sense that good crystal oscillator clocks do. Possibly not what TimePod is really designed for?
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A further indication that something is wrong could be coming from this plot:
Coming from here: Sound quality limitations of Raspberry Pi + I2S DACs - DACs - Volumio
Coming from here: Sound quality limitations of Raspberry Pi + I2S DACs - DACs - Volumio
Attachments
You have published a phase noise plot, the Timepod is designed for phase noise measurements.
Anyway, if you have read all my posts I have clearly said several times that the FifoPi is "a decent device sold at a reasonable and honest price", but it's not the "ultimate" device.
One should be careful when using certain terms.
Anyway, if you have read all my posts I have clearly said several times that the FifoPi is "a decent device sold at a reasonable and honest price", but it's not the "ultimate" device.
One should be careful when using certain terms.
Hi Ian,
I have access to multiple Phase noise measurement equipment from the lastest model TimePod to full Agilent systems..
I'd be happy to verify the PN measurements and if the measurements are confirmed I can diagnose the cause and rectify... I work n such designs on a daily basis..
During this Covid lockdown I located in Europe if anyone wants to send me a board to independently verify...
Ian,
In the case of the scope, as it had been mentioned before, the lower part of the phase noise spectrum is altered by the applied PLL algorithm.
And so the contribution of this part of the spectra is decreased, when the total jitter is calculated. So it can be very probable that Your read-out of jitter displayed by the routine is not corrisponding with the values obtained from a more correct low frequency presentation of the spectra.
So I don't think one can trust too much the numerical value obtained, and it should be always too 'optimistic', because of the low frequency cut..
Ciao, George
George,
sorry, but I don't understand, if you don't think one can trust too much the numerical value obtained then what is the meaning of the jitter measurement?
The result of the measurement is just the standalone number, it does not show the spectrum of the noise.
@Ian
It would be very useful setting the time division to 50 ns in the "LRCK after FifoPi analog view".
sorry, but I don't understand, if you don't think one can trust too much the numerical value obtained then what is the meaning of the jitter measurement?
The result of the measurement is just the standalone number, it does not show the spectrum of the noise.
@Ian
It would be very useful setting the time division to 50 ns in the "LRCK after FifoPi analog view".
Thanks JohnW for the kind offering. I'm glad you have both time domain and phase domain equipment to access. I'll send you a FifoPi for measurements. I'll PM you later.
Good weekend.
Ian
It's not only a low frequency cut because of the short time series,
it's also a resolution cut with the 8 bit ADCs and their time base.
I have an Agilent 8GSPS 8 bit scope myself, but I would never
ever look upon it as a replacement for my TimePod, where
4 14/16? bit ADCs must work for > 1h to average their own
noise contributions away in the 3-cornered hat, as well as the
contribution of the correlated-out 2 crystal oven time bases.
I'm willing to do tests if someone sends me a DUT.
Timepod on short notice, E5052B and the new 300K€ R&S
machine require 2*280 Km of driving, so that would take
some lead time until I happen to drive there for a good reason,
such as being paid for something else.
cheers, Gerhard
it's also a resolution cut with the 8 bit ADCs and their time base.
I have an Agilent 8GSPS 8 bit scope myself, but I would never
ever look upon it as a replacement for my TimePod, where
4 14/16? bit ADCs must work for > 1h to average their own
noise contributions away in the 3-cornered hat, as well as the
contribution of the correlated-out 2 crystal oven time bases.
I'm willing to do tests if someone sends me a DUT.
Timepod on short notice, E5052B and the new 300K€ R&S
machine require 2*280 Km of driving, so that would take
some lead time until I happen to drive there for a good reason,
such as being paid for something else.
cheers, Gerhard
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@andrea_mori
1.
I don't see any jitter, I measure the phase noise, I have calculate the jitter using a converter.
As I said several time I don't care about jitter since it's a standalone number without the noise spectrum, useless for me.
You continue arguing about LRCK, but the phase noise plot tells that you have even higher noise floor in the SCK.
For your convenience, forgive for a while the LRCK since you don't trust the measurement with the Timepod at low frequency, but you have the identical noise floor issue at a frequency (12.288 MHz) where the reliability of the Timepod is indisputable.
Can you explain the reason?
You still not answer my question "Why can't you see the 590.4ps time domain random jitter and deterministic jitter in your phase domain measurement?"
If you can not see jitter, you should see something in phase noise.
2.
Because if you change the integrating bandwidth the jitter change too.
As you can see it's an arbitrary value, while the phase noise plot is absolute, it shows exactly the noise in dB of all the sideband.
You can't argue an absolute value, while you can argue an arbitary value.
Integration bandwidth has nothing to do with my time domain measurement.
To convert phase noise plot into phase jitter, you need to integrate the full bandwidth to make it equivalent to time jitter. If the bandwidth is not enough, the calculated phase jitter number will be smaller. But in your case it is opposite, the RMS 66.19ps calculated phase jitter number was much bigger than the 7.68ps time jitter. You didn't give us any explanation.
3.
Because the noise floor of the output is very high, I suspect it's due to the crosstalk.
Why this crosstalk?
Are you using the PLL of the FPGA?
Have you took a look at the waveform before the D-FF?
What noise floor do you mean? jitter noise floor? logic level noise floor? or measurement noise floor?
I myself is an audiophile. I didn't use any PLL in FPGA. FifoPi FPGA logic is slaved to the MCLK. FifoPi is implemented in synchronized logic architecture for the best possible low jitter performance.
Clock time jitter is deviation of a clock edge from itsideal location. I suspect you convert the LRCK into sine wave before you feed into TimePod with clock edge information lost. DAC relies on edge of clock to perform conversion, not the sine wave.
You still not answer my question "The huge difference in time jitter before and after FifoPi can be directly seen from the analog waveforms, why we can not find the difference in your phase noise plot."
Good weekend.
Ian
1.
I don't see any jitter, I measure the phase noise, I have calculate the jitter using a converter.
As I said several time I don't care about jitter since it's a standalone number without the noise spectrum, useless for me.
You continue arguing about LRCK, but the phase noise plot tells that you have even higher noise floor in the SCK.
For your convenience, forgive for a while the LRCK since you don't trust the measurement with the Timepod at low frequency, but you have the identical noise floor issue at a frequency (12.288 MHz) where the reliability of the Timepod is indisputable.
Can you explain the reason?
You still not answer my question "Why can't you see the 590.4ps time domain random jitter and deterministic jitter in your phase domain measurement?"
If you can not see jitter, you should see something in phase noise.
2.
Because if you change the integrating bandwidth the jitter change too.
As you can see it's an arbitrary value, while the phase noise plot is absolute, it shows exactly the noise in dB of all the sideband.
You can't argue an absolute value, while you can argue an arbitary value.
Integration bandwidth has nothing to do with my time domain measurement.
To convert phase noise plot into phase jitter, you need to integrate the full bandwidth to make it equivalent to time jitter. If the bandwidth is not enough, the calculated phase jitter number will be smaller. But in your case it is opposite, the RMS 66.19ps calculated phase jitter number was much bigger than the 7.68ps time jitter. You didn't give us any explanation.
3.
Because the noise floor of the output is very high, I suspect it's due to the crosstalk.
Why this crosstalk?
Are you using the PLL of the FPGA?
Have you took a look at the waveform before the D-FF?
What noise floor do you mean? jitter noise floor? logic level noise floor? or measurement noise floor?
I myself is an audiophile. I didn't use any PLL in FPGA. FifoPi FPGA logic is slaved to the MCLK. FifoPi is implemented in synchronized logic architecture for the best possible low jitter performance.
Clock time jitter is deviation of a clock edge from itsideal location. I suspect you convert the LRCK into sine wave before you feed into TimePod with clock edge information lost. DAC relies on edge of clock to perform conversion, not the sine wave.
You still not answer my question "The huge difference in time jitter before and after FifoPi can be directly seen from the analog waveforms, why we can not find the difference in your phase noise plot."
Good weekend.
Ian
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Ian,
Great - Looking forward to running the tests... maybe theirs somebody "local" in Europe who can loan a board for testing... not sure if I've got a RPi - but I can order one.
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