ostripper said:
Good morning OS,
I'm not saying that they are wrong, just to take the results with a grain of salt, especially if you have used the same models in each sim.
Likewise for compensation. The sim will give a close approximation and show the effect of different compensation schemes. It will not hit the nail on the head though, as it doesn't use real devices, on a real board in a real environment. Too many other variables.
Gotta go...
Os,
looks good, I was wondering why you were neglecting cfp as input, wonder why the 5th is not coming down too, strange, you can manupulate the spectrum a little with the cfp in the input, the higher the current through the first transistor the more ....... eheh
you experiment, youll be learning something useful.
H3 is not that bad, amp tends to sound more detailed, but dont have it above H2, again subjective preference but try get rid anything else after H3. At these THD levels you can only really hear any difference at higher powers. Another reason why I think carlos finds class a muffled, it drops H3 plenty with relation to H2.
I would recommend a jfet in the input for the cfp, there is high voltage jfets available if you take the trouble to seach for them so no cascode required upto a certain voltage. There are some issues with using the jfets like this but compromises have to be made. The jfets have a more relaxed sound, strangely enough they raise H3 and odd order more than anything else.
looks good, I was wondering why you were neglecting cfp as input, wonder why the 5th is not coming down too, strange, you can manupulate the spectrum a little with the cfp in the input, the higher the current through the first transistor the more ....... eheh
you experiment, youll be learning something useful.H3 is not that bad, amp tends to sound more detailed, but dont have it above H2, again subjective preference but try get rid anything else after H3. At these THD levels you can only really hear any difference at higher powers. Another reason why I think carlos finds class a muffled, it drops H3 plenty with relation to H2.
I would recommend a jfet in the input for the cfp, there is high voltage jfets available if you take the trouble to seach for them so no cascode required upto a certain voltage. There are some issues with using the jfets like this but compromises have to be made. The jfets have a more relaxed sound, strangely enough they raise H3 and odd order more than anything else.
I haven't done clipping tests yet.
I'm using LTSpice IV 4.00i, Normal solver.
Now that I look, I do see some evidence of instability with a 1KHz square wave - the negative going edge displays some evidence of oscillation.
I'm sure with the right refinements, this topology can be made to work. The Cyrus One amp itself sounds excellent, although perhaps part of the stability is the relatively slow output devices it uses.
I've uploaded the Cyrus Two schematic for a reference (same as Cyrus One with only a few elements changed and double outputs).
I'm using LTSpice IV 4.00i, Normal solver.
Now that I look, I do see some evidence of instability with a 1KHz square wave - the negative going edge displays some evidence of oscillation.
I'm sure with the right refinements, this topology can be made to work. The Cyrus One amp itself sounds excellent, although perhaps part of the stability is the relatively slow output devices it uses.
I've uploaded the Cyrus Two schematic for a reference (same as Cyrus One with only a few elements changed and double outputs).
An externally hosted image should be here but it was not working when we last tested it.
ostripper said:
I assume you're talking about this amp below?
An externally hosted image should be here but it was not working when we last tested it.
I hate to keep repeating this, but this is another configuration that requires the "full up" loop gain probe of the LTspice loopgain2.asc in the LTspice examples\Educational directory. It seems you've been avoiding using this technique. I'm guessing you're hung up on some aspect of how to proceed with it? If so, and you give me some hints as to where you're having trouble, I can walk you through it. It's really not as bad as it looks.
BTW, the loop gain probe in the picture above is the simplified one, and it's also in the wrong location. One must use the "full up" probe and technique, and put the probe between the base of Q2 and the left side of C1. This is because C1 forms a nested feedback loop from the VAS output back to the amp's inverting input. Whoever put this graphic up is simulating the loop gain incorrectly.
Just moving V5 to the location I mentioned above will not fix the problem. One must use the "full up" loop gain probe as per loopgain2.asc.
Looking back on this, I should never have mentioned the audioamp.asc example. It's pretty accurate for the specific application it addresses, but it cannot be generalized to the case where you put the probe in some arbitrary position.
No, andy...I did loopgain 2 on my amp and had the pleasure of seeing my darlington VAS gain plot individually.A successful endeavor.
I simmed the amp above and had to 'fix it" to simulate
reliably.. it broke out in oscillation very easily, one thing
I did was remove C1, and I added a little degen at LTP.
basically it is the first design of the FA2 with CFP inputs so
It was easy to tame.
I created a text file with the comments as to be able to
"plug it in" on any design...
I did not do the one above!!!!
OS
I simmed the amp above and had to 'fix it" to simulate
reliably.. it broke out in oscillation very easily, one thing
I did was remove C1, and I added a little degen at LTP.
basically it is the first design of the FA2 with CFP inputs so
It was easy to tame.
I created a text file with the comments as to be able to
"plug it in" on any design...
I did not do the one above!!!!
OS
ostripper said:
Hmm, okay. But what you posted here as the result is not the loopgain2.asc technique. That's what threw me off. I can tell because of the -V(d)/V(c) expression. loopgain2.asc uses both voltage and current injection (Ii and Vi) and uses this formula for the loop gain:
-1/(1-1/(2*(I(Vi)@1*V(x)@2-V(x)@1*I(Vi)@2)+V(x)@1+I(Vi)@2))
If that's what you did (but just didn't post the result), then all is well. If not, then it's not the full-up loop gain simulation. If you try the technique and formula above and have problems with it, I can help with that.
BW product - confused
http://www.diyaudio.com/forums/attachment.php?s=&postid=1700312&stamp=1230796339
shows unity gain ~ 800kHz, where the phase margin is >80degrees.
Why does this and all the other discrete gain plots show unity gain as close to 1MHz.
I thought at least some of these designs would be around the Leach value of 8MHz. Or is his unity gain bandwidth measured differently?
http://www.diyaudio.com/forums/attachment.php?s=&postid=1700312&stamp=1230796339
shows unity gain ~ 800kHz, where the phase margin is >80degrees.
Why does this and all the other discrete gain plots show unity gain as close to 1MHz.
I thought at least some of these designs would be around the Leach value of 8MHz. Or is his unity gain bandwidth measured differently?
Re: BW product - confused
Hi Andrew,
What Leach quotes is the gain-bandwidth product. The unity loop gain frequency (where |AB| = 1) is approximately the gain bandwidh product divided by the nominal closed-loop gain set by the feedback resistors.
Edit: Another way of looking at this is that the gain-bandwidth product is the frequency at which |A| extrapolates to 1, assuming single-pole response. Thus they differ by B, which is the feedback resistor divider ratio.
AndrewT said:[Why does this and all the other discrete gain plots show unity gain as close to 1MHz.
I thought at least some of these designs would be around the Leach value of 8MHz. Or is his unity gain bandwidth measured differently?
Hi Andrew,
What Leach quotes is the gain-bandwidth product. The unity loop gain frequency (where |AB| = 1) is approximately the gain bandwidh product divided by the nominal closed-loop gain set by the feedback resistors.
Edit: Another way of looking at this is that the gain-bandwidth product is the frequency at which |A| extrapolates to 1, assuming single-pole response. Thus they differ by B, which is the feedback resistor divider ratio.
Andy,
if the gain of these amps we're analysing were all +20dB (10times) then the GBW product would be in the range 8MHz to 12MHz. Is that correct?
Now that I am there, what do I do with the unity loop gain graph to check stability?
Do I find where Gain intersects with Plot and read off frequency and at that frequency read off the phase to be subtracted from 180degrees?
Or should I be using the GBW product graph to extract the phase margin?
if the gain of these amps we're analysing were all +20dB (10times) then the GBW product would be in the range 8MHz to 12MHz. Is that correct?
Now that I am there, what do I do with the unity loop gain graph to check stability?
Do I find where Gain intersects with Plot and read off frequency and at that frequency read off the phase to be subtracted from 180degrees?
Or should I be using the GBW product graph to extract the phase margin?
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