Don't look at GND_Clean look at the noisy GND, the chip splits nicely down the middle, the dirty GND is on the right the clean GND is on the left. So the split if already there you just have to do the layout so the dirty and clean loops don't overlap...
There are similar devices from TI with evaluation boards, what I do when doing these sort of layouts is look at all the options and get as many examples as possible.
There is ONE GND only you just have to ensure that current loops do not overlap or interact. The digital signals in really need to run over a RETURN path, and that is the best way of thinking about GND, it is the signals RETURN path.
Away from my work machine so cant get to examples at the moment, if I get more time today I will try and dig out a recent TI device I am working on the layout for. Keep the solution simple, break the design down, you have a dirty side and a clean side, they have to join so you have to think where, you can but a moat (split) in the return path plane (GND) and join the dirty side to the clean side under the device... The techniques are similar to those you would use for a SMPS layout, if you are doing class D layout then read as many app. notes and design guides for different SMPS's layouts etc, they are the same, just that a class D is a modulated switch mode... I also did a thread on EMC issues with switching designs with notes and hints from Kieth Armstrong.
http://www.diyaudio.com/forums/power-supplies/193705-switcher-emc-design.html
http://www.analog.com/media/en/anal...cing-ground-bounce-in-dc-to-dc-converters.pdf
As I have said will try and find examples if possible...
There are similar devices from TI with evaluation boards, what I do when doing these sort of layouts is look at all the options and get as many examples as possible.
There is ONE GND only you just have to ensure that current loops do not overlap or interact. The digital signals in really need to run over a RETURN path, and that is the best way of thinking about GND, it is the signals RETURN path.
Away from my work machine so cant get to examples at the moment, if I get more time today I will try and dig out a recent TI device I am working on the layout for. Keep the solution simple, break the design down, you have a dirty side and a clean side, they have to join so you have to think where, you can but a moat (split) in the return path plane (GND) and join the dirty side to the clean side under the device... The techniques are similar to those you would use for a SMPS layout, if you are doing class D layout then read as many app. notes and design guides for different SMPS's layouts etc, they are the same, just that a class D is a modulated switch mode... I also did a thread on EMC issues with switching designs with notes and hints from Kieth Armstrong.
http://www.diyaudio.com/forums/power-supplies/193705-switcher-emc-design.html
http://www.analog.com/media/en/anal...cing-ground-bounce-in-dc-to-dc-converters.pdf
As I have said will try and find examples if possible...
Thanks Pafi/Marce for your feedback. I'll digest this and come back to you. TNT - There are some readings on the Sure site
Sure Electronics' webstore 2 x 500 Watt Class D Audio Amplifier Board -T-AMP
I'm hoping to improve on those figures with careful selection of components. The bypass caps are a mile away from the IC on that design. See some pics here.
Gremlin- kleiner Class-T Amp- ganz groß. - Seite 19 - DIY-HIFI-Forum
I picked up a recon UPL 16 with B29 digital board. If all goes well I will be able to test the digital amps I now make.
Sure Electronics' webstore 2 x 500 Watt Class D Audio Amplifier Board -T-AMP
I'm hoping to improve on those figures with careful selection of components. The bypass caps are a mile away from the IC on that design. See some pics here.
Gremlin- kleiner Class-T Amp- ganz groß. - Seite 19 - DIY-HIFI-Forum
I picked up a recon UPL 16 with B29 digital board. If all goes well I will be able to test the digital amps I now make.
I've been toying with open loop amps this week. Sometimes you just have to have a go and see what happens. The fundamental idea is from a chinese amp but with faster components.
PWM into SN74ABT541B - ultrafast non inverting buffer.
http://www.ti.com/lit/ds/symlink/sn74abt541b.pdf
AO4612 - 60V complementary reasonably fast trench mosfets with
http://www.aosmd.com/pdfs/datasheet/AO4612.pdf
Wired for a single supply. It could be terrible. We'll see.
My PWM dev environment is the old MSI Diva Live with Intersil DAE-3 dsp on board. The black edge card socket above the IC has the PWM output from the dsp as well as i2s I/O. I have the MSI 5.1 amplifer and the 7.1 pre amp cards that connect into the D2. I might be changing op amps and modding the hell out of that.
PWM into SN74ABT541B - ultrafast non inverting buffer.
http://www.ti.com/lit/ds/symlink/sn74abt541b.pdf
AO4612 - 60V complementary reasonably fast trench mosfets with
http://www.aosmd.com/pdfs/datasheet/AO4612.pdf
Wired for a single supply. It could be terrible. We'll see.
My PWM dev environment is the old MSI Diva Live with Intersil DAE-3 dsp on board. The black edge card socket above the IC has the PWM output from the dsp as well as i2s I/O. I have the MSI 5.1 amplifer and the 7.1 pre amp cards that connect into the D2. I might be changing op amps and modding the hell out of that.
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qfn with thermal pad soldering
a diy method that worked well for me:
- drill a 3mm hole at the pcb location corresponding to the qfn center (was a 6.1 x 6.1 qfn in my case)
- with a round-shape grinding stone make the hole bigger on the ground plane side (to make it easier to solder the qfn ground pad)
- solder the qfn (no problems to do hand-soldering if the contacts extend to the qfn side else reflow or hot air)
- on the ground plane side add solder to the qfn pad
- solder a piece of desoldering braid to connect the ground plane to the qfn pad (I used 2 pieces of desoldering braid placed as a cross)
a diy method that worked well for me:
- drill a 3mm hole at the pcb location corresponding to the qfn center (was a 6.1 x 6.1 qfn in my case)
- with a round-shape grinding stone make the hole bigger on the ground plane side (to make it easier to solder the qfn ground pad)
- solder the qfn (no problems to do hand-soldering if the contacts extend to the qfn side else reflow or hot air)
- on the ground plane side add solder to the qfn pad
- solder a piece of desoldering braid to connect the ground plane to the qfn pad (I used 2 pieces of desoldering braid placed as a cross)
You're right. It should be an inverting part. I spotted the SN74LV540ADGVR. A small TVSOP with 6V tolerant I/O. The higher the Vgs the better the performance at the fet.
TP3 = TP2
TP4 = NOT TP1
TP5 = TP1
TP6 = NOT TP2
The parallel and cascade develops the correct positive and negative inputs into the fets. This is so we can can use a single rail supply. That's the theory anyway. Correct me if I am wrong! This is a bit of a diversion adventure.
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The next step is determining what kind of gate waveform timing you need to control the FETs, what kind of timing you get from the PWM modulator, and how you can convert the existing to the desired one.
Basically all output FETs inverts the signal in the corrected topology, so a half bridge (p and n channel = Hi and Low side) needs gate waveforms with the same polarity, but you may need dead time to avoid cross-conduction. This may be included in PWM H and L, but I don't recommend to use this capability. I tell you why:
While you can set the correct gate polarity of one half-bridge and keep the dead-time, with the other half-bridge you need inverted operation, but this inversion (if done on PWM H and L signals) will turn dead-time to cross-conduction. So dead time in PWM H and L should be avoided if you want to use them controlling full bridge.
Dead time should be set at each gate independently. After you make this, you will have many different possibilities to determine control scheme. Including ClassBD modulation, if your modulator support this.
Gate dead timing can be done with a D, R, C network, this can be either after the gate driver or before gate driver, each has its own benefit.
Always try to draw waveforms before building! This is easier than debugging a non-operational, and not understood circuit.
Basically all output FETs inverts the signal in the corrected topology, so a half bridge (p and n channel = Hi and Low side) needs gate waveforms with the same polarity, but you may need dead time to avoid cross-conduction. This may be included in PWM H and L, but I don't recommend to use this capability. I tell you why:
While you can set the correct gate polarity of one half-bridge and keep the dead-time, with the other half-bridge you need inverted operation, but this inversion (if done on PWM H and L signals) will turn dead-time to cross-conduction. So dead time in PWM H and L should be avoided if you want to use them controlling full bridge.
Dead time should be set at each gate independently. After you make this, you will have many different possibilities to determine control scheme. Including ClassBD modulation, if your modulator support this.
Gate dead timing can be done with a D, R, C network, this can be either after the gate driver or before gate driver, each has its own benefit.
Always try to draw waveforms before building! This is easier than debugging a non-operational, and not understood circuit.
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I do professional designs where this method is unacceptable to the inspection criteria, also all boards are reflowed properly, something that can be done by the DIYer quite cheaply using simple electronic ovens, some good threads covering this on here. Not having the correct PCB structure under these pads seriously diminishes the ability to remove heat from these sort of devices. Also these devices can be reworked and soldered using a hot air gun, again allowing for a proper PCB structure under the pad, I will try and dig out some more info, but a search on reworking bottom terminated components may get some results.
I've been layout out a few options for the stereo BTL STA516BE.
The output nets/loops are roughly the same length to within around 2mm. Ground plain is uninterrupted. I'm not sure about the inductors and leaving long traces after them before the filters.
Board size 110mm x 60mm.
Input - PWM each pin separated by GND.
Output - 4 pole Neutrik SpeakOn.
Not quite finished but any WIP comments are welcomed.
The output nets/loops are roughly the same length to within around 2mm. Ground plain is uninterrupted. I'm not sure about the inductors and leaving long traces after them before the filters.
Board size 110mm x 60mm.
Input - PWM each pin separated by GND.
Output - 4 pole Neutrik SpeakOn.
Not quite finished but any WIP comments are welcomed.
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Sgpu,
Not bad! Long traces of the inductor is not a big problem. Everything is OK, although there are some things that can be optimized further. Input GND and power GND loops could have been separated (shielded) better from each other, most easily by a series of GND " stiching" vias underneath the IC. 10-20 pcs.
And take care of heat sink fastening screws! Close to IC. The potential of heatsink should be power GND, ("dirty GND") hence don't make direct contact to case!
Not bad! Long traces of the inductor is not a big problem. Everything is OK, although there are some things that can be optimized further. Input GND and power GND loops could have been separated (shielded) better from each other, most easily by a series of GND " stiching" vias underneath the IC. 10-20 pcs.
And take care of heat sink fastening screws! Close to IC. The potential of heatsink should be power GND, ("dirty GND") hence don't make direct contact to case!
I wouldnt follow the recommended filter schematic. The benefit of series config of 100 nF is that this way only one of them have to be foil type. Since you use foil capacitors in all position you don't need this feature and it would be more effective if you tied C24 (etc...) directly to output node. But resistors must be much bigger, they will dissipate really high power when you drive it near 20 kHz (or with square wave).
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