Project Moshulu : a journey into class D

[sgpu]

Gouging the motions on stackup and how to route PWM.

Firstly, a possible change to 4 layer stackup.

Option 1:
Via to PWM pins to bottom plane. Inductance? PWM routed on bottom, layer 3 ref 5 mil prepreg up.

Option 2:
PWM on top plane with no via intruptions to headers with layer 2 ref being a 5mil prepreg down.

To reduce crosstalk separate traces by 3 x trace width or further maybe with guard trace between.

 

[sgpu]

In other news. Mouser has a good deal on these moulded 6.3V 330uF polymer caps. Half the price of Digikey.
http://www.mouser.co.uk/ProductDetail/Murata-Electronics/ECASD90J337M009K00/

 

[doctormord]

Guard trace is so 1990...

(Is crosstalk on PWM really an issue? (With schmitt-trigger inputs) I'd would more think of conductor reflexion.)

 

[Pafi]

Guard trace is so 1990...

(Is crosstalk on PWM really an issue? (With schmitt-trigger inputs) I'd would more think of conductor reflexion.)

Of course impedance matching must be assured first. But crosstalk definitely can cause more problem then some uV of digital supply noise.

I wrote this in post #39:

Logic level signal tracing is an other thing. Although it is digital, the timing errors in it are analogue by nature, and signal transition imperfections causes timing error (jitter). The jitter tolerance in such system is incredibly low if you want to achieve the theoretical resolution capabilities. Full scale: 2 us -> -100 dB = 20 ps. If you have eg. 100 mV uncorrelated disturbance during transition, and despite of this you want to limit timing error to 20 ps, then you need a signal slew rate of 5V/ns, which is achievable, but then you need impedance matched routing and significant track separation, (and high speed interconnect cables if modulator is on separate board).

This roughly 100 mV limit applies to crosstalk, considering the other parameters are typical for this setup.

 

[Pafi]

sgpu!

Calculate impedances first! Source and interconnect, and input capacitance of power stage. Do they match? Simulate transient response! Is it monotonous? Is it fast enough? Then check what track width you need to achieve this on your different routing layers!

 

[sgpu]

Thanks for the heads up Pafi!

 

[sgpu]

Another option I've been toying with is skipping the off board approach and head towards a motherboard system and fit 9 mono amps or line outs in a approx 1u format. Then open source the card specs. Something like this.

An externally hosted image should be here but it was not working when we last tested it.

An externally hosted image should be here but it was not working when we last tested it.

 

[marce]

Guard traces need to be wide or they can add more problems than they solve...

 

[sgpu]

Status update. Routing the i2s lines into the top row of headers (J10-13). Getting messy. I hope to tidy this up a bit over the weekend.

 

[800DR]

Hi SPGU

What'sup

 

[Mark Tillotson]

[ About the EPC2903 modules ]

This board basically forms a LGA module (Land Grid Array) soldering these to your base board can be tricky even with a proper reflow oven, also the complexity of the mother board in terms of thermal considerations would be quite costly with filled micro vias, better as stated to use a simpler solution.

I found it straightforward to solder these in a homebrew reflow oven, treat just as any other SMT part with moderate to high thermal capacity, and fill the thermal vias with solder paste. The board underside can be reflowed again and sanded and fixed to a heatsink if wanted.

https://epc-co.com/epc/Portals/0/epc/documents/guides/EPC9201_qsg.pdf