Oppo's BDP105 - discussions, upgrading, mods...

I do not know exactly what the circuit shown by abraxalito does, but I suppose it works in analogue domain, and maybe DAC post processing.

Quite correct - its the output buffer for my current DAC (called 'free radical') with enough current ability to drive IEMs direct.

With analog circuits not running pure classA its the high frequency noise on the supply from the output stage switching that's the killer. It goes into the ultrasonic but is overall much lower in freq than for a digital chip. Hence total capacitance matters much more than a few nH of series inductance.
 
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Quite correct - its the output buffer for my current DAC (called 'free radical') with enough current ability to drive IEMs direct.

With analog circuits not running pure classA its the high frequency noise on the supply from the output stage switching that's the killer. It goes into the ultrasonic but is overall much lower in freq than for a digital chip. Hence total capacitance matters much more than a few nH of series inductance.

Thanks for explanations.
If there is about a current output buffer, then I think that only few hundreds µF you have in your ceramics tower it may not be enough... Instantaneous current needs it may be higher than what your ceramics can deliver. Current pulse response (specially for the low end of the spectre) it may be much better when using larger capacity in that place. But this depend on what PSU you use. If about a shunt regulator, then it may be a different approach.
I should use there few thousands µF (in case of a voltage regulator). But such capacity is not easy to get from ceramics... So some other cap types it should be used.
 
If there is about a current output buffer, then I think that only few hundreds µF you have in your ceramics tower it may not be enough...

You are right - I don't only use ceramics. That pic I showed was taken when the build wasn't complete. As I mentioned, on the finished board I also have lots of electrolytics which are placed either side of the components in the pic. If I'd taken a pic of the completed board, the detail of the capacitor stack would be largely obscured by the surrounding capacitors.

Incidentally its not just the instantaneous current demands which call for lots of capacitance - the SQ in the lower frequencies benefits too even at lower signal levels. In practice I have about 50,000uF and I don't know if further improvements can be gained by going higher. I was limited by the size of the PCB. I suppose I could try stacking lytics next....:p
 
for any decoupling application inductance is the killer and stray parasitic inductance can make your decoupling totally useless. The determining factor for high speed digital design is the signal rise time, and the knee frequency derived from this. Look up all the documentation on decoupling and you will see that minimising inductance is more critical that ultimate capacitance value...
On the Oppa I believe there are 50MHz clocks so yes 1mm is critical in decoupling applications, and on a cap stack like this would render the stack pointless due to parasitic inductance....
Remember for digital decoupling parasitic inductance must be minimised.

I would imagine a better way of doing this is with a few caps placed around an
area of concern connecting power and ground planes using very short and
even multiple vias. But you are definitely the expert here on this topic, so all
ears on this one!

I'm wondering why a lot of these very high speed chips don't have decoupling
built in. It would appear the chips internal lead wires themselves would have
some part in spoiling the party - so to speak.
 
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You are right - I don't only use ceramics. That pic I showed was taken when the build wasn't complete. As I mentioned, on the finished board I also have lots of electrolytics which are placed either side of the components in the pic. If I'd taken a pic of the completed board, the detail of the capacitor stack would be largely obscured by the surrounding capacitors.

Incidentally its not just the instantaneous current demands which call for lots of capacitance - the SQ in the lower frequencies benefits too even at lower signal levels. In practice I have about 50,000uF and I don't know if further improvements can be gained by going higher. I was limited by the size of the PCB. I suppose I could try stacking lytics next....:p

Yes, right about SQ. Also right about going to high with these capacities. I can see that yo are high enough...:D The large place needed it may be a problem. We are on the same side on this...:)
 
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I would imagine a better way of doing this is with a few caps placed around an
area of concern connecting power and ground planes using very short and
even multiple vias. But you are definitely the expert here on this topic, so all
ears on this one!

I'm wondering why a lot of these very high speed chips don't have decoupling
built in. It would appear the chips internal lead wires themselves would have
some part in spoiling the party - so to speak.

You are welcome with your "imagination". There it may not be only one "expert" limit in this thread...:)
 
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I would imagine a better way of doing this is with a few caps placed around an
area of concern connecting power and ground planes using very short and
even multiple vias. But you are definitely the expert here on this topic, so all
ears on this one!

I'm wondering why a lot of these very high speed chips don't have decoupling
built in. It would appear the chips internal lead wires themselves would have
some part in spoiling the party - so to speak.

They do these days, or have some very small caps placed on the BGA interposter. I have placed very small SMD ceramics between pads on a BGA, using HDI PCB layout techniques, with a top ground plane and the next layer down the power layer. With 0.1 dielectric between the layers and stacked micro vias you get the minimum loop area and thus minimum inductance.
Decoupling is providing the art of supplying a devices power, with minimum effect on the power and ground signals. Power supply to a device is like a bucket brigade, the on chip capacitance comes first, then PCB inter plane capacitance (this is more effective than decoupling caps, and modern designs will have minimal dielectric between power layers to increase this capacitance), then the very small caps next to the pins, then the larger reservoir caps further away and finally the PSU. For decoupling near the pins you always pick the smallest case size for the chosen value of capacitor, and route between them using the lowest inductive way (and thus smallest loop area) possible.

Fas42, there is also Eric Bogatin, Howard Johnson, Ralph Morrison, Douglas Brooks and numerous data sheets and application notes provided by every chip manufacturer, some of these tomes can run into quite a few pages just on decoupling. There is also the people who specialise in high speed layout and all it entails who advise and do layouts for military/aerospace and other critical designs, who can give you some practical advise from lots of experience doing this. My own reference library for all aspects of PCB design runs to two DVD's now.

The very first thing you should read if you are going to play with high speed design is this:
The 10 Best Ways to Maximize Emission from Your Product

Coris, I was saying that multiple low inductance devices are better than one device with long leads of long PCB traces, the inductance does not decrease with a stack, but increases due to the increased distances involved.
 
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Coris, I was saying that multiple low inductance devices are better than one device with long leads of long PCB traces, the inductance does not decrease with a stack, but increases due to the increased distances involved.

I see that you have a clue in what you say...;) Here is of course right, and I agree. I was also thinking that for such application (quite low frequency range analogue device) a little gap between caps, to make it easy to then desolder it, It may not be so critical for the device quality decoupling...:)
 
Hi, Joe,

I'm currently designing my next experimental DAC and considering the possible utilization of some elements of your Oppo player mods. Regarding use of the OPA-860, I see that you drive it in a differential voltage amplification (common-emitter) mode rather than the common-base current mode others typically apply toward DAC I/V duty. However, the datasheet predicts alarmingly poor THD figures in the common-E mode, particularly, for the third harmonic spec. of -57dB (without an emitter degeneration resistor, I believe).

What sort of distortion harmonics and levels are you seeing generated by the OPA-860 in your suggested differential voltage amplification circuit? Thanks.
 
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IV converter

Ken,

I wouldn't be too concerned about that third harmonic distortion number because it's measured at 5 MHz… In any case Joe did promise that he would provide measurements for this circuit.

Personally, I decided to go with the SEN discrete IV circuit described here:

http://www.diyaudio.com/forums/digi...-sen-evolution-minimalistic-iv-converter.html

You can download the original linear audio article for free now from their site. This looks very appealing, although it does require floating 18 V battery power supplies.

Eric
 
Hi, Joe,

I'm currently designing my next experimental DAC and considering the possible utilization of some elements of your Oppo player mods. Regarding use of the OPA-860...

Give me a couple of days and I will furnish you some distortion measurements and you can judge for yourself.

I think you should build it - I think you will be pleased with it... but I will do that distortion measurement.

Cheers, Joe