I have finally managed to unearth the information that Motorola Toulouse sent me in 1995. The attached picture of a TO-3P and its thermal response at least makes it clear that the transistor is constructed by soldering the die directly onto the metal part that faces the outside world, and there are no preforms or whatever to complicate things.
Unfortunately the temperature graphs are an object lesson in non-communication. All the axes are logarithmic, presumably to turn exponentials into straight lines, and each temperature line has a different scale. The top of the chip seems to start off at less than 1 degC, while the bottom face of the copper starts off just below 10 degC. We apparently have an infinite isothermal heatsink, but no idea what temperature it is at, unless the zero at bottom right means it is at 0 degC. If so, we have an 89 degC drop across the mica washer, which seems highly unlikely.
If the temperatures at far right can be trusted at all, they seem to say that the junction is 4 degC hotter than the top of the copper, and 5 degC hotter than the bottom of the copper. I have grave doubts about the temperatures but at least the construction is clear.
Unfortunately the temperature graphs are an object lesson in non-communication. All the axes are logarithmic, presumably to turn exponentials into straight lines, and each temperature line has a different scale. The top of the chip seems to start off at less than 1 degC, while the bottom face of the copper starts off just below 10 degC. We apparently have an infinite isothermal heatsink, but no idea what temperature it is at, unless the zero at bottom right means it is at 0 degC. If so, we have an 89 degC drop across the mica washer, which seems highly unlikely.
If the temperatures at far right can be trusted at all, they seem to say that the junction is 4 degC hotter than the top of the copper, and 5 degC hotter than the bottom of the copper. I have grave doubts about the temperatures but at least the construction is clear.
Attachments
Another nugget of info from Toulouse. The attached picture shows the stresses undergone by a power transistor chip during construction. How it withstands those temperatures I do not know. The bottom right picture clearly shows that the chip is completely immersed in plastic, and it does not sit in a void.
Now we know why the tops of transistors get so hot. Anybody got any info on the thermal resistance and specific heat of the plastic used for this??
Now we know why the tops of transistors get so hot. Anybody got any info on the thermal resistance and specific heat of the plastic used for this??
Attachments
I'd guess those scales are in percent of final value of the temperature drop from that point to the infinite isothermal heatsink - and in that case they do make sense. 89 probably means the temperature from mica washer top to heatsink has reached 89% of its final value after 10 seconds and the 94 at top means the chip has reached 94% of the final value after 10 seconds.
The missing 6% is then caused by heat still flowing into the package.
89 degrees C drop over the mica washer at *10W* doesn't make any sense at all.
The missing 6% is then caused by heat still flowing into the package.
89 degrees C drop over the mica washer at *10W* doesn't make any sense at all.
megajocke said:I'd guess those scales are in percent of final value of the temperature drop from that point to the infinite isothermal heatsink - and in that case they do make sense. 89 probably means the temperature from mica washer top to heatsink has reached 89% of its final value after 10 seconds and the 94 at top means the chip has reached 94% of the final value after 10 seconds.
The missing 6% is then caused by heat still flowing into the package.
89 degrees C drop over the mica washer at *10W* doesn't make any sense at all.
I did think that might be it, but one of the vertical scales is labelled in degrees C.
(mica insulator with 9k/W thermal resistance for example...)Transient Thermal Impedance
The attached LTspice thermal simulation is one that I did previously for an IRFP240 vertical power MOSFET. That device has a dc thermal resistance of 0.83 C/W and is likely not too far off from what a ThermalTrak transistor would look like.
Transient Thermal Impedance (TTI) describes the peak rise of junction temperature due to a pulse of power being applied to the junction. It takes into account the distributed thermal impedance and thermal inertia of the device. In the simulation below, a 10ms 1-watt pulse (1 amp is the electrical analog) is applied, and the junction temperature is seen to rise by 0.42 C at Vout (voltage is the electrical analog of temperature). For a 10ms single pulse, the transient thermal impedance is thus 0.42 C/W.
This model was constructed by matching the transient thermal impedance curves provided in the IRFP240 data sheet over about six decades of pulse time. The non-uniform distributed transmission line-like structure is due to the three-dimensional nature of the heat flow out from the junction. In many devices, the source of heat flow is like a very large number of small point sources distributed across the surface area of the die. If the heat flow was one-dimensional, the model would look more like a uniform transmission line.
R1 – R4 and C1 – C4 model the heat flow in the silicon die, which is the dominant source of thermal resistance. R5, C5, R6 and C6 model the heat flow in the copper header. In this model, 0.1 C/W of the total thermal resistance is allocated to the copper header. Because R6 is returned to thermal ground, this simulation models the device as being attached to an infinite heat sink.
The header heat flow is crudely modeled with the assumption of a local thermal region where the die is located and a larger heat-spreading region corresponding to the larger total area of the copper header.
In this model, a ThermalTrak diode attached to the copper header next to the transistor die would be modeled as having its temperature as that existing at the junction of R5 and R6. The thermal resistance to the diode and the thermal inertia of the diode are assumed to be insignificant. In other words, the junction temperature of the diode is assumed to be the same as that of the local area of the copper header to which it is attached, both on a steady-state and transient basis.
The dominant thermal time constant of the model is about 17 ms. This means that the junction temperature of the transistor reacts and changes quite quickly. It is especially important to recognize that, while a significant temperature differential may exist in steady state between the transistor and diode junctions during significant transistor power dissipation, the temperature of the transistor junction will relax quickly to nearly that of the copper header with a time constant of only about 17ms, when power is removed.
Cheers,
Bob
The attached LTspice thermal simulation is one that I did previously for an IRFP240 vertical power MOSFET. That device has a dc thermal resistance of 0.83 C/W and is likely not too far off from what a ThermalTrak transistor would look like.
Transient Thermal Impedance (TTI) describes the peak rise of junction temperature due to a pulse of power being applied to the junction. It takes into account the distributed thermal impedance and thermal inertia of the device. In the simulation below, a 10ms 1-watt pulse (1 amp is the electrical analog) is applied, and the junction temperature is seen to rise by 0.42 C at Vout (voltage is the electrical analog of temperature). For a 10ms single pulse, the transient thermal impedance is thus 0.42 C/W.
This model was constructed by matching the transient thermal impedance curves provided in the IRFP240 data sheet over about six decades of pulse time. The non-uniform distributed transmission line-like structure is due to the three-dimensional nature of the heat flow out from the junction. In many devices, the source of heat flow is like a very large number of small point sources distributed across the surface area of the die. If the heat flow was one-dimensional, the model would look more like a uniform transmission line.
R1 – R4 and C1 – C4 model the heat flow in the silicon die, which is the dominant source of thermal resistance. R5, C5, R6 and C6 model the heat flow in the copper header. In this model, 0.1 C/W of the total thermal resistance is allocated to the copper header. Because R6 is returned to thermal ground, this simulation models the device as being attached to an infinite heat sink.
The header heat flow is crudely modeled with the assumption of a local thermal region where the die is located and a larger heat-spreading region corresponding to the larger total area of the copper header.
In this model, a ThermalTrak diode attached to the copper header next to the transistor die would be modeled as having its temperature as that existing at the junction of R5 and R6. The thermal resistance to the diode and the thermal inertia of the diode are assumed to be insignificant. In other words, the junction temperature of the diode is assumed to be the same as that of the local area of the copper header to which it is attached, both on a steady-state and transient basis.
The dominant thermal time constant of the model is about 17 ms. This means that the junction temperature of the transistor reacts and changes quite quickly. It is especially important to recognize that, while a significant temperature differential may exist in steady state between the transistor and diode junctions during significant transistor power dissipation, the temperature of the transistor junction will relax quickly to nearly that of the copper header with a time constant of only about 17ms, when power is removed.
Cheers,
Bob
Attachments
Are you sure R4, C4 "belong" to the die?
A die of 5x5x0.3mm will only have about 12mJ/k thermal capacity while if R4,C4 and everything to the left is in the die it would need to have 36mJ/k. Or is the die this much bigger? Doesn't make much difference though for the application, those 0.4k/W would be the mounting of it and the copper just below it, not accessible for a temperature sensor.
A die of 5x5x0.3mm will only have about 12mJ/k thermal capacity while if R4,C4 and everything to the left is in the die it would need to have 36mJ/k. Or is the die this much bigger? Doesn't make much difference though for the application, those 0.4k/W would be the mounting of it and the copper just below it, not accessible for a temperature sensor.
megajocke said:
I have assumed that they do belong to the die, but I freely admit that the model was constructed to fit the IR transient thermal impedance curves with only an heuristic approach to the physical construction.
There are many assumptions built into making such models. For example, one of my assumptions was allocating 0.1 C/W to the copper header and all the rest to the silicon and its attach. An even more important assumption is that the IR TTI curve is correct. It is likely that the IR folks arrived at this curve through use of a finite element model, like FlowTherm, augmented by some pulsed power measurements. They probably had to do some hand-waiving as well.
The most important thing is the dominant thermal time constant. I think that if only the estimated 12mJ/k thermal capacity was used in a conventional lumped/distributed model, and knowing what the dc thermal resistance is, one would end up with a too-small dominant thermal time constant.
Note also that for many devices we do not enjoy the luxury of a published TTI curve. However, one can infer to some extent the dominant thermal time constant by taking a look at the SOA curves at voltages below where secondary breakdown effects come into play. The pulse width where the SOA begins to increase substantially above the dc value can give a rough clue as to the dominant thermal time constant.
Bottom line, there is necessarily a lot of hand-waiving and SWAG estimating here, but it is far better than nothing.
Cheers,
Bob
Crossover distortion and biasing dynamics
When we discuss thermal bias compensation, we are mainly addressing crossover distortion (but also bias stability). We all know that in theory we want 26 mV across the emitter resistor for a Class AB BJT amplifier. We also know that in practice this does not always hold exactly. We also know that with a Vbe temperature coefficient of 2.2 mV/C, it does not take a lot of C’s of mis-racking to move us substantially away from that 26 mV number.
ThermalTrak transistors transform an almost impossible problem into a difficult one that still does not have a really clean solution. They do get us thermally closer to the junction, but still further away than we wish.
Suppose we build an amplifier with +/- 35V rails that clips at 60W into 8 ohms. Assume it uses a single pair of 150W ThermalTrak output transistors with 0.83 C/W thermal resistance to case. As in my model, assume about 0.7 C/W from BJT junction to the header, and assume that the diode is at the header temperature. Now run the amplifier at 1 kHz or above at 1/3 power (20 watts) into 8 ohms. Each output transistor will dissipate about 14 watts.
Under these continuous power dissipation conditions, we will drop about 0.7 X 14C = 10C from the BJT junction to the tracking diode, causing potentially 22 mV of bias voltage mis-tracking. This SWAG does not depend to first order on the thermal insulator drop or the size of the heat sink. It just concerns the thermal drop from the BJT junction to the tracking diode junction. This is about the best we can do with ThermalTraks; what we can do with conventional transistors is usually far worse.
The good news with ThermalTraks is that when the source of dissipation goes away in a quiet interval, the BJT junction temperature gets back to that of the header and tracking diode with a fairly fast time constant of only about 17 ms. Given the high crest factor of music, we may be able to conclude that the tracking is not too bad most of the time.
This all does, however, bring up the issue of bias-setting methodology.
Consider two options for setting the bias adjustment. The first is that we let the amplifier idle and warm up for an hour, then adjust the bias for 26 mV (or whatever we think the right number is – it will often be a bit less) across the emitter resistors. With this approach, under continuous high-power conditions (like at 1/3 power at 1 kHz) the output stage will become over-biased and gm-doubling will come into play. However, when the power is removed or substantially reduced, the short die time constant of 17 ms or so will quickly bring the bias back to a point where the BJT junction and diode junction are tracking fairly well (because no large heat flow is occurring from the BJT junction).
Another well-intentioned option to set up the bias might be to adjust for lowest THD at 1/3 power (this represents the opposite extreme) after the amplifier has gotten really toasty. Here the bias will be “right” for the continuous high-dissipation case, but when a quiet interval happens the short thermal time constant of the BJT die will drive the amplifier into a seriously under-biased condition. Not what we want.
A compromise approach might be to make the adjustment at a few watts, where there is not too much error caused by heat flow from the BJT junction.
Finally, all of this makes a good case for using more, rather than fewer, output transistor pairs, independent of SOA and beta droop considerations. Then the errors caused by heat flow from the BJT junction to the copper header will be smaller.
Crossover distortion is an insidious form of distortion, and I often wonder if dynamic bias mis-tracking contributes to some amplifiers sounding different in practice even though they measure about the same on the bench.
Cheers,
Bob
When we discuss thermal bias compensation, we are mainly addressing crossover distortion (but also bias stability). We all know that in theory we want 26 mV across the emitter resistor for a Class AB BJT amplifier. We also know that in practice this does not always hold exactly. We also know that with a Vbe temperature coefficient of 2.2 mV/C, it does not take a lot of C’s of mis-racking to move us substantially away from that 26 mV number.
ThermalTrak transistors transform an almost impossible problem into a difficult one that still does not have a really clean solution. They do get us thermally closer to the junction, but still further away than we wish.
Suppose we build an amplifier with +/- 35V rails that clips at 60W into 8 ohms. Assume it uses a single pair of 150W ThermalTrak output transistors with 0.83 C/W thermal resistance to case. As in my model, assume about 0.7 C/W from BJT junction to the header, and assume that the diode is at the header temperature. Now run the amplifier at 1 kHz or above at 1/3 power (20 watts) into 8 ohms. Each output transistor will dissipate about 14 watts.
Under these continuous power dissipation conditions, we will drop about 0.7 X 14C = 10C from the BJT junction to the tracking diode, causing potentially 22 mV of bias voltage mis-tracking. This SWAG does not depend to first order on the thermal insulator drop or the size of the heat sink. It just concerns the thermal drop from the BJT junction to the tracking diode junction. This is about the best we can do with ThermalTraks; what we can do with conventional transistors is usually far worse.
The good news with ThermalTraks is that when the source of dissipation goes away in a quiet interval, the BJT junction temperature gets back to that of the header and tracking diode with a fairly fast time constant of only about 17 ms. Given the high crest factor of music, we may be able to conclude that the tracking is not too bad most of the time.
This all does, however, bring up the issue of bias-setting methodology.
Consider two options for setting the bias adjustment. The first is that we let the amplifier idle and warm up for an hour, then adjust the bias for 26 mV (or whatever we think the right number is – it will often be a bit less) across the emitter resistors. With this approach, under continuous high-power conditions (like at 1/3 power at 1 kHz) the output stage will become over-biased and gm-doubling will come into play. However, when the power is removed or substantially reduced, the short die time constant of 17 ms or so will quickly bring the bias back to a point where the BJT junction and diode junction are tracking fairly well (because no large heat flow is occurring from the BJT junction).
Another well-intentioned option to set up the bias might be to adjust for lowest THD at 1/3 power (this represents the opposite extreme) after the amplifier has gotten really toasty. Here the bias will be “right” for the continuous high-dissipation case, but when a quiet interval happens the short thermal time constant of the BJT die will drive the amplifier into a seriously under-biased condition. Not what we want.
A compromise approach might be to make the adjustment at a few watts, where there is not too much error caused by heat flow from the BJT junction.
Finally, all of this makes a good case for using more, rather than fewer, output transistor pairs, independent of SOA and beta droop considerations. Then the errors caused by heat flow from the BJT junction to the copper header will be smaller.
Crossover distortion is an insidious form of distortion, and I often wonder if dynamic bias mis-tracking contributes to some amplifiers sounding different in practice even though they measure about the same on the bench.
Cheers,
Bob
I good read ,Bob. The "swag" as you named it shows
itself from Vbias HS mounting to direct device mounting (I've gone
as far as to put the Vbe in a hole underneath
touching the "slug" of the OP device) so I can see where the next level (t-traks) would bring it.
Definitely!! I don't have T-traks, but Vbias placement,Vq
sensitivity have impact on sound.
OS
showsitself from Vbias HS mounting to direct device mounting (I've gone
as far as to put the Vbe in a hole underneath
touching the "slug" of the OP device) so I can see where the next level (t-traks) would bring it.
Definitely!! I don't have T-traks, but Vbias placement,Vq
sensitivity have impact on sound.
OS
ostripper said:I good read ,Bob. The "swag" as you named it
itself from Vbias HS mounting to direct device mounting (I've gone
as far as to put the Vbe in a hole underneath
touching the "slug" of the OP device) so I can see where the next level (t-traks) would bring it.
Definitely!! I don't have T-traks, but Vbias placement,Vq
sensitivity have impact on sound.
OS
Thanks, ostripper.
BTW, "SWAG" stands for "Scientific Wild @ssed Guess".
.Cheers,
Bob
Re: Crossover distortion and biasing dynamics
If we consider steady state, during idle condition there is still power dissipated. The delta T can be compensated by including a fixed voltage in the bias.
If there is a step in power, the thermal model in steady state is a resistor divider and the temperature of the copper will be proportional to the temperature of the BJT junction. This can be taked into account by an adjustable tempco in the Vbe multiplier. Of course during transients, the mistracking will be large and signal dependend but correct in steady state.
If this is correct, one approach to bias adjustment couldbe to adjust the Vbias at llow power and adjust the tempco at high power.
What do you think of the remark of CH. Hansen saying that the diode tracking should not be too fast ( so too good) to avoid bias modulation by the low frequency content of the music?
As you said, parallel transistors at the output will increase accuracy and electronic crossovers will make the medium and high amplifiers more free from transient tracking problems.
JPV
Bob Cordell said:
If we consider steady state, during idle condition there is still power dissipated. The delta T can be compensated by including a fixed voltage in the bias.
If there is a step in power, the thermal model in steady state is a resistor divider and the temperature of the copper will be proportional to the temperature of the BJT junction. This can be taked into account by an adjustable tempco in the Vbe multiplier. Of course during transients, the mistracking will be large and signal dependend but correct in steady state.
If this is correct, one approach to bias adjustment couldbe to adjust the Vbias at llow power and adjust the tempco at high power.
What do you think of the remark of CH. Hansen saying that the diode tracking should not be too fast ( so too good) to avoid bias modulation by the low frequency content of the music?
As you said, parallel transistors at the output will increase accuracy and electronic crossovers will make the medium and high amplifiers more free from transient tracking problems.
JPV
My interpretation of the graph in post #401 from Douglas is this:
The graph shows no absolute temperature but a delta T as the graph is labled DT(°C). That means before the step in power dissipation from 0 to 10W the temperature rise is 0.
Indeed the final temperature of 94°C temperature rise is a bit confusing - the graph does not note what thermal sink is used and what temperature it has. If mica has something like 0.71W/mK a 200um thick isolation on a TO3-P case with 15x20mm has a Rth of 0,939 °K/W and thus @10W => dT is 9,39°K. So heatsink temperature was Theatsink = Tcopper -dTmica = 89°K - 9,39°K ~ 80°K. At 10W power the Rth of the heatsink was a poor 8K/W.
At second the straight lines on algarithmic scale indicate something like a time constant for the thermal response on a stepwise change in power dissipation (like a RC time constant).
The first graph I would read something like 4°K/1ms for the SI region. Unfortunately the scaling is lousy.
Michael
The graph shows no absolute temperature but a delta T as the graph is labled DT(°C). That means before the step in power dissipation from 0 to 10W the temperature rise is 0.
Indeed the final temperature of 94°C temperature rise is a bit confusing - the graph does not note what thermal sink is used and what temperature it has. If mica has something like 0.71W/mK a 200um thick isolation on a TO3-P case with 15x20mm has a Rth of 0,939 °K/W and thus @10W => dT is 9,39°K. So heatsink temperature was Theatsink = Tcopper -dTmica = 89°K - 9,39°K ~ 80°K. At 10W power the Rth of the heatsink was a poor 8K/W.
At second the straight lines on algarithmic scale indicate something like a time constant for the thermal response on a stepwise change in power dissipation (like a RC time constant).
The first graph I would read something like 4°K/1ms for the SI region. Unfortunately the scaling is lousy.
Michael
Re: Re: Crossover distortion and biasing dynamics
While it is true that under high power there is effectively a resistor divider for temperature from the junction to the copper header, the vexing problem is that if we take that into account by multiplying the diode tempco, we then have a problem when the high-dissipation interval stops, because the junction temperature quickly relaxes to that of the copper, but the copper has a much larger time constant.
I have thought about what Hansen said, and it is an interesting concern. In the same vein, I have at times wondered if one incurs a problem when using only one diode from one polarity of output transistor, as opposed to one from each polarity. The reason being that the dissipation of each transistor has a somewhat half-wave rectified nature to it. At very low frequencies, symmetry considerations would argue that both halves of the waveform dissipation should be taken into account (even though any presence of such a bias modulation might be objectionable).
The key thing to bear in mind here is that the thermal time constant at issue in this regard is not that of the junction, but rather that of the copper header. Bias modulation by low frequency program content will be filtered by that longer time constant.
However, lets not forget that the instantaneous variations of the junction temperature with program-induced variations in dissipation does itself modulate the bias condition. This is largely unavoidable, and it operates at the thermal time constant of the junction, so is more susceptible to low-frequency program content.
I guess if I had my druthers, I'd have the tracking diode be intimate with the BJT junction, and if that arrangement created problems by being too fast, I'd find a way to filter its effects with some sort of external R-C arrangement.
Cheers,
Bob
JPV said:
While it is true that under high power there is effectively a resistor divider for temperature from the junction to the copper header, the vexing problem is that if we take that into account by multiplying the diode tempco, we then have a problem when the high-dissipation interval stops, because the junction temperature quickly relaxes to that of the copper, but the copper has a much larger time constant.
I have thought about what Hansen said, and it is an interesting concern. In the same vein, I have at times wondered if one incurs a problem when using only one diode from one polarity of output transistor, as opposed to one from each polarity. The reason being that the dissipation of each transistor has a somewhat half-wave rectified nature to it. At very low frequencies, symmetry considerations would argue that both halves of the waveform dissipation should be taken into account (even though any presence of such a bias modulation might be objectionable).
The key thing to bear in mind here is that the thermal time constant at issue in this regard is not that of the junction, but rather that of the copper header. Bias modulation by low frequency program content will be filtered by that longer time constant.
However, lets not forget that the instantaneous variations of the junction temperature with program-induced variations in dissipation does itself modulate the bias condition. This is largely unavoidable, and it operates at the thermal time constant of the junction, so is more susceptible to low-frequency program content.
I guess if I had my druthers, I'd have the tracking diode be intimate with the BJT junction, and if that arrangement created problems by being too fast, I'd find a way to filter its effects with some sort of external R-C arrangement.
Cheers,
Bob
Re: Re: Re: Crossover distortion and biasing dynamics
I still have a problem:
Let suppose that we start from idle. The junction is seeing some bias power dissipated and its temperature is above the one of copper and diode in proportion to the thermal resistance dividers.
The heatsink is at another stable temperature below the others.
Then we apply a step of power. After vanishing of die and solder transients, the die, copper (so the diode) and heatsink will experience the long time constants of copper and heatsink but in the same manner. Although all the temperatures are still drifting, the die and diode temperature remain at proportional temperatures, the coef of proportionnality is set by the thermal resistor dividing action.. The same will happen on cooling after removing of the signal power until we reach the temperatures set by the bias dissipation. The transients of the die will induce mistraking but the transients induced by the copper and heatsink will be applied to both.
If this is correct the tuning of the tempco can compensate for this and the mistracking will happen only during the short time constant of the die. It is the delta T that matters.
Am I wrong ?
JPV
Bob Cordell said:
I still have a problem:
Let suppose that we start from idle. The junction is seeing some bias power dissipated and its temperature is above the one of copper and diode in proportion to the thermal resistance dividers.
The heatsink is at another stable temperature below the others.
Then we apply a step of power. After vanishing of die and solder transients, the die, copper (so the diode) and heatsink will experience the long time constants of copper and heatsink but in the same manner. Although all the temperatures are still drifting, the die and diode temperature remain at proportional temperatures, the coef of proportionnality is set by the thermal resistor dividing action.. The same will happen on cooling after removing of the signal power until we reach the temperatures set by the bias dissipation. The transients of the die will induce mistraking but the transients induced by the copper and heatsink will be applied to both.
If this is correct the tuning of the tempco can compensate for this and the mistracking will happen only during the short time constant of the die. It is the delta T that matters.
Am I wrong ?
JPV
Here's some more data on the NJL4281/4302. The attached scope capture shows the thermal time constant between the diode and the transistor's Vbe.
No attempt was made to match tempcos as the purpose of this test was to measure how fast the diode would respond to temperature changes in the transistor.
This test was performed with two curve tracers. One was supplying the compensation diode with a 10 mA constant current. The other tracer was driving the transistor. The transistor was ounted on a heatsink.
The two traces are the diode's Vf and the transistor's Vbe as temperature increases due to a 3A step in collector current.
As you can see, the diode responds rather quickly...
John
No attempt was made to match tempcos as the purpose of this test was to measure how fast the diode would respond to temperature changes in the transistor.
This test was performed with two curve tracers. One was supplying the compensation diode with a 10 mA constant current. The other tracer was driving the transistor. The transistor was ounted on a heatsink.
The two traces are the diode's Vf and the transistor's Vbe as temperature increases due to a 3A step in collector current.
As you can see, the diode responds rather quickly...
John
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