Newbie LM3886 Circuit

[simonra]

Here's the updated layout; I've added R8, R4(Rf2) & C5(Cf). The way it is at the moment I've got a pretty long loop (SPKR+ -> R4 -> C5 -> Vin-).

If that looks like it'll be a problem I'll have to shuffle a lot of the components about to find room. I'm thinking of moving the speaker out connector to the top of the board and taking HBR with it. Perhaps also moving C6 down to the bottom right so I can snug C7 up against C8 - does that sound like a good plan?

 

[simonra]

And here's version 10 of the layout, does that look better?

 

[tomchr]

Suggestion on Rev. 10: Instead of using a trace to connect C4 to the input ground plane, why not just extend the plane north in the layout and scoot C4 over? That would give you lower ESR and ESL on C4. As I've said before... You're paying for the copper anyway. You might as well use it.

I plan to solder Cc directly across the input pins on the underside of the pcb - that's why it's disappeared from the layout.

Why? The whole point of getting a PCB made is that you avoid point-to-point and fly-by-wire components. There's plenty of room for Cc. For example, you could rotate C2 and place Cc next to R6.

I have to admit that I'd completely confused myself about Rf2 and Cf and also mis-read the responses in this thread.

If you add Cc, you'll get overshoot in the transient response. Rf2 and Cf tame this overshoot.

When you say to add the resistor to the "outside" of the input cap does that mean between the signal input to the board (the molex connector) and the cap?

"Outside" would be the source side of the input cap. So across the Molex input connector.

Be mindful of the spacing on the thermal reliefs. If you push the limits on the supply voltage, you'll have 84 V between nodes in places. Now, I'm not suggesting you run your circuit at those voltages, but I would at least make sure the board doesn't arc over before the ABS MAX limit on the IC is reached.

For my recommendations on the supply voltage, have a look here: Taming the LM3886 - Output Power.

Tom

 

[simonra]

Suggestion on Rev. 10: Instead of using a trace to connect C4 to the input ground plane, why not just extend the plane north in the layout and scoot C4 over? That would give you lower ESR and ESL on C4. As I've said before... You're paying for the copper anyway. You might as well use it.Tom

The trace to C4 is from R5, making up the zobel network (the net label didn't show up on the bmp export).

Why? The whole point of getting a PCB made is that you avoid point-to-point and fly-by-wire components. There's plenty of room for Cc. For example, you could rotate C2 and place Cc next to R6.Tom

You are completely correct of course - C13(Cc) slotted in with the minimum of effort. Thanks.

Be mindful of the spacing on the thermal reliefs. If you push the limits on the supply voltage, you'll have 84 V between nodes in places. Now, I'm not suggesting you run your circuit at those voltages, but I would at least make sure the board doesn't arc over before the ABS MAX limit on the IC is reached.Tom

I hadn't realised the polygon line width in Eagle dictates the size of the thermal reliefs - I'd reduced the line widths and not noticed the effect. I've tried to get a decent amount of copper to the pads now.

It feels like I'm getting close to finishing the design now. I've attached the latest version with the updates noted above - BTW the image file makes it look as though the PWR- and GND planes overlap to the bottom left of C11, this is not the case - DRC is reporting no errors.

A couple of quick questions - I over ordered the 10,000uF power supply caps, would there be any benefit in doubling them up?

Also I ended up getting ones rated at 63V and I'm a bit worried I should have gone bigger - from a 2x25V 300VA I'm expecting ~38V on the rails - do you think I've left enough of a safety margin?

Thanks,
Simon.

 

[AndrewT]

There is a rule for implementing ground and/or power planes that no cut in a plane should pass under a current carrying component.
Turn that around: No component that carries a current should pass across the cut between two planes.

Look at HBR, C4, R5, and maybe R3.
If any current passes through one of those components, what route does the current take to get back to the source? Does that route forced by the cut in the plane now include a big loop area?

 

[simonra]

There is a rule for implementing ground and/or power planes that no cut in a plane should pass under a current carrying component.
Turn that around: No component that carries a current should pass across the cut between two planes.

Look at HBR, C4, R5, and maybe R3.
If any current passes through one of those components, what route does the current take to get back to the source? Does that route forced by the cut in the plane now include a big loop area?

I'm trying to get my head around this... for example HBR bridges Signal Ground and Power Ground and the way I've laid the board out means that theres a gap between the two planes beneath the resistor. So should I have ended each plane at the pads of the resistor essentially placing the whole component within the gap?

The graphic of the layout has ditched some of the labelling, so just for clarity the there are four separate planes on the bottom layer: signal ground meets power ground at HBR; Power- is the plane to the bottom right and the plane in the centre is the IC output. From the graphic it looks as though power- and power ground meet to the bottom left of C11, however in the layout they remain separated.

Thanks,
Simon.

 

[AndrewT]

You need to find the current route for HBR.
Then decide whether that loop area is causing any performance degradation.
You need to repeat that process for every component that passes across a cut in a plane.

If you want a plane to operate as an impedance reducing technique, then that plane should be continuous, preferably with few, or tiny perforations.
The plane should provide a path for the return current to pass along/under/over the whole flow route as the current returns to the source.

I do not know how to design for power planes, so any advice I give is as a bystander who knows effectively nothing.
If you don't know how to design power planes, then I suggest you don't adopt bad versions.

 

[simonra]

Okay, so to test my understanding (or lack thereof): HBR provides a route from the Speaker- to Vin- and also from Signal Return to Power Ground. I'm guessing the former is the most critical in terms of routing. So the flow of current I should be interested in is between the Speaker Ground and the Vin- pin on the IC. There's a large distance between HBR and Vin- so I need to look at whats stopping me from getting it closer and decide which components take priority.

Also by 'cut in a plane' do you mean a gap between two different planes or a cut creating a gap in a single plane... if you know what I mean?

Thanks,
Simon.

 

[OlegSh]

Comments to the layout in post #64.

R5, C4 are part of the output and should be routed on top of the output GND. Now they are on top of the signal GND.

You can improve your design if you make capacitor lead pitch smaller. If I interpreted the current layout correctly you have selected 3.5mm pitch 22uF electrolytic caps but you can easily get such with 2.5mm pitch. Same for the ceramic (4.7uF) caps. You can easily get 1uF and 2.2 uF MLCCs with 2.54mm pitch (100VDC rating). The 470uF caps can be 5 mm lead pitch and 10~12mm diameter. This can increase the performance of your circuit and make your layout much tighter.

I recommend increasing restrict area around mounting holes to prevent shorting of various potentials to chassis by mounting screws and standoffs.

Some comments for better use of Eagle output. You can hide the Drills layer since it does not provide useful information for us. Also increase resolution in the export->image dialog to something like 200~300 dpi. This should produce better looking design pictures and will make it easier to follow.

 

[AndrewT]

..............
Also by 'cut in a plane' do you mean a gap between two different planes or a cut creating a gap in a single plane... if you know what I mean?

Thanks,
Simon.

this applies to any gap between two planes if the current is flowing from one plane to the other.
And also applies to a single plane where you have introduced a cut, or gap.

Imagine you have single uncut ground plane.
Now pass a trace on a separate layer connecting a source to a load.
The return current will want to take the lowest impedance route.
At LF that impedance does not care much about inductance and the lowest impedance route becomes the lowest resistance route. That means the shortest route through the thickest/widest copper.
At HF the inductance become dominating. Now the current needs to find the lowest inductance route to return the current to source. This is usually by following a line in the ground plane directly underneath the FLOW trace and components. The line is quite wide, the highest current density is directly under the Flow trace, the lowest current density is some distance away from the Flow route. There are intermediate current densities varying from directly under to a big distance away from that directly under.

Now introduce a gap/cut in that plane that is across that FLOW route. The return current is forced to find a new longer route. And worse the new route includes a BIGGER Loop Area. Impedance has been increased.

The sole purpose of the power and ground planes is to minimise interference and it does this by minimising the impedance.
Anything you do that increases the impedance reduces the performance of the ground/power plane.

 

[simonra]

Comments to the layout in post #64.

R5, C4 are part of the output and should be routed on top of the output GND. Now they are on top of the signal GND.

Thanks. I've moved both over to the right hand side of the board.

You can improve your design if you make capacitor lead pitch smaller. If I interpreted the current layout correctly you have selected 3.5mm pitch 22uF electrolytic caps but you can easily get such with 2.5mm pitch. Same for the ceramic (4.7uF) caps. You can easily get 1uF and 2.2 uF MLCCs with 2.54mm pitch (100VDC rating). The 470uF caps can be 5 mm lead pitch and 10~12mm diameter. This can increase the performance of your circuit and make your layout much tighter.

I agree, I should have spent a bit more time taking footprint size into account when selecting components. Unfortunately I jumped the gun and almost all of these components are sitting on my desk. I think I'll go with what I've got for now and learn from that for my next build.

Some comments for better use of Eagle output. You can hide the Drills layer since it does not provide useful information for us. Also increase resolution in the export->image dialog to something like 200~300 dpi. This should produce better looking design pictures and will make it easier to follow.

Hopefully the attached image looks a bit better.

Thanks,
Simon.

 

[simonra]

AndrewT,
Thanks for your thorough explanation in post #70, very useful information. I'll see if I can apply it.

 

[simonra]

This time without the drills.

 

[scottjoplin]

Okay, so to test my understanding (or lack thereof): HBR provides a route from the Speaker- to Vin-

no

and also from Signal Return to Power Ground.

yes

 

[tomchr]

The sole purpose of the power and ground planes is to minimise interference and it does this by minimising the impedance.
Anything you do that increases the impedance reduces the performance of the ground/power plane.

I'll tag team on that message, and add that more precisely the purpose of planes is to minimize the voltage drop across them. A plane is the lowest impedance connection you can get. This means the I*R (or I*Z) drop is the lowest. In some cases this results in less interference, but for audio and other precision "DC" circuits, the advantage of planes is in the lower I*R drop itself as this drop introduces an error voltage (say difference between signal ground and power ground), which wrecks the performance of your circuit. I quantified this in the LM3886 PCB vs P2P thread, which I suggest looking through.

So the best approach would be to have a solid ground plane for the power ground and another solid plane for the signal ground. Now you're into a 4-layer board and your manufacturing cost just tripled. Great...!
To get the data sheet performance of the LM3886 there's no need for 4-layer boards, though I have occasionally wondered if one could get better than the data sheet performance by going that route. For the LM3886, the best option is to have as much of the area available for planes consumed by the power ground plane. That plane carries the largest current, hence needs the lowest impedance to minimize the IR drop. The signal ground plane can be tiny as it carries relatively little current.
I see two ways to separate the planes on the same layer:

1. Moating: I.e. slots or breaks in the ground plane to create an island or peninsular for the signal ground.
2. Careful layout: The majority of the current will flow along the shortest path between two points. If you place the components carefully, you can actually make that path pretty short. This will result in a section of the ground plane which will be relatively quiet. Place your sensitive circuitry there. In that case the plane will be completely solid.

In the LM3886DR, I actually did both and get performance that's a touch better than what's shown in the data sheet for the LM3886. Some of that improvement may just be improvements in instrumentation. I'm sure my AP APx525 audio analyzer is better than the AP System One or System Two used by National at the time.

Tom

 

[tomchr]

Why's C6 so enormous? It only sees about 3 V during operation and can easily be a 6.3 V cap.

Why not pull the power ground plane over to cover the top end of HBR? You'd get less inductance that way. There're also huge areas under C3, C5, R4, and R5 that could be flooded and drive the impedance of the planes down further. It's like you have an aversion against planes or something... I've said it before and I'll say it again: The board manufacturer charges the same regardless of how much of the copper you use. Use as much as possible!

Tom

 

[scottjoplin]

Have a look at the way Mark has used the copper here, post #27 2 Separate Transformers

 

[simonra]

Thanks all for your help again.

I'm finding that I need to read things through about six times before they start to sink in so I'm still absorbing the information in the suggested threads. In the mean time, I've finally decided not to spare the copper, so the bottom is now just one big plane for the power ground; top left is the signal ground and the two on the right are pwr+/-.... better / worse?

Simon.

 

[tomchr]

I like the supply routing a lot better now. The signal ground around R4 won't do you much good as it's cut off by the northern pad of R4. There's nothing wrong with what you have but you could optimize it a bit further. One suggestion would be to use a pour on the output connection as well. It carries quite a bit of current, so some copper is needed. You have some room to play with under R4 and R5. Just be careful not to eat too much into the supply pour. You might also be able to shorten the output net a tad if you rotate the speaker connector 90 º CCW.

I suggest rotating C4 180º to minimize the impedance from its ground connection to the power ground star, which is somewhere on the ground plane in the middle of all the decoupling caps. You should have plenty of room if you scoot C4 closer to C7. You might even be able to scoot it south and put it next to R5. That'd be about as tight as you'd get.

I'd take the chamfered corners out of the ground pours up where it says SPKR.

I like the routing of the MUTE signal a lot better now.

I openly admit that my suggestions are approaching diminishing returns.

Tom

 

[simonra]

Thanks Tom,

Phew... it feels like I'm getting somewhere. I ought to stop flooding the site with slowly evolving images of my layout, but here's another one (it looks like there's a short between PWR+ and output pin but there's a gap in Eagle and it passes DRC)... I'm getting ready to hit the order button.

Simon.