My version of the G = 1000 low noise measurement amp (for Ikoflexer)

Difference to the Groner ?
Patrick

30u foil/66Meg input coupling, common source FET stage, 50...100 mOhm in sources
for feedback. NPN cascode, active load. Transimpedance stage with ada4898, fb taken
from here, gain = 60 dB to this point. I could not get it stable with 50 dB.

The many FETs pose a input cap. problem. Cgs is largely removed by the feedback to
the sources.

Cgd Miller does not apply because of Cascode, TIA cannot do that alone.
The base of the Cascode-NPN gets a level-shifted version of the input signal,
so the AC across Cgd is zero. (Bootstrap)

There is an integrator to generate the negative gate voltage. A window comparator
checks if we are close to the chosen operating point. If we are not, the gate resistor
is reduced from 66 to 4.7 Meg to speed up settling.

That would otherwise take forever. Lower corner of the passband is 0.1 Hz, goes
up to 1, maybe 2 MHz.

1/f corner is 30 Hz for IF3602, 1KHz for BF862. Some of the new FETs from
ON Semi may have a 40 Hz corner, have ordered them.

LTspice simulation says that 4 IF3602 pairs could reach 95 pV/rt Hz above 30 Hz;
That requires abt. 250 mA Id, not too excessive for 8 transistors.

The 50 mOhm source resistor is the largest noise contributor after the FETs, then the
cascode transistor and then the active load. Spice really helped through the
iterations to peel this onion.

Let's see how it works in reality.
 
> Some of the new FETs from ON Semi may have a 40 Hz corner, have ordered them.

This one ?

http://www.onsemi.com/pub_link/Collateral/NSVJ5908DSG5-D.PDF
Patrick

Looks good, probably the same process.

I have ordered

NSVJ3910SB3T1G
NSVJ3557SA3T1G
2SK2394-6-TB-E
MCH3914-8-TL-H

Should fit into BF862 sockets.

There is at least one more, but back ordered.
Also, at Mouser, the data sheet links seem to be somewhat messed up.
Newfangled stuff.

Gerhard

ps
Can't we get a moderator to move this thread to a place where it fits?
 
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The ones you listed are all variations of ex-Sanyo products if I am not wrong.
(CPH3910, 2SK3557, 2SK2394, MCH3914)


The moderator moved it here because I was supposed to be selling PCBs as a commercial operation.
So they even wanted to move this and others to the Vendors' bazzar.
I managed to persuade them that a few PCBs for friends is never commercially viable.
Which is why we ended up here, as a compromise.

Someone other than me have to lobby them to change their mind.


Sorry for that,
Patrick
 
> How much work <.1nV using straight forward circuit topologies would be

I guess you already have some ideas in your mind ?

Patrick

About the same...
LTspice simulation says that 4 IF3602 pairs could reach 95 pV/rt Hz above 30 Hz;
That requires abt. 250 mA Id, not too excessive for 8 transistors.

Beyond that auto-correlating or fancy chopper techniques. As for MC phono-pre it's a good question, I suspect the input capacitance of 8 of those FET's is problematic even for MC, not sure though. IIRC 5 or 6nF total ?
 
Beyond that auto-correlating or fancy chopper techniques. As for MC phono-pre it's a good question, I suspect the input capacitance of 8 of those FET's is problematic even for MC, not sure though. IIRC 5 or 6nF total ?

But you can bootstrap away the capacitance. The source follows the gate because of the feedback; that would be even more precise in a real follower.
Also, one can make the drain follow the gate by kicking the base of the cascode, so
there is no capacitive current between G and D.

That works only because the signal through the cascode is a current and the
absolute voltage levels there are less important (attenuated by beta).
I was really surprised that decoupling of the cascode base divider brings
absolutely nothing, same goes for the bias current source.

If the cascode was a conveyor belt, one would modulate only slightly the location where
the coal hits the belt; that has no first order influence on throughput.

Phil Hobbs & Win Hill in sci.electronics.design do a lot of cap-killing bootstraps; I have
not yet understood all of their tricks, but I'm working on it. :)

The metal box I have made has place for 2 pre amps so I can use it with cross correlation
in phase noise measurements. The LIGO guys are somewhat handicapped wrt cross cor.
They would need, say, 100 equal solar systems and pop one every 10 seconds.. :D
 
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The LIGO guys are somewhat handicapped wrt cross cor.
They would need, say, 100 equal solar systems and pop one every 10 seconds.. :D

I guess the resistance on MC is low, we have had some issues with cap neutralization and noise pumping. And then there is induced gate current noise, but again it's probably not an issue at these low source impedances. The AD8610 and AD743 both required mask revs for one or the other. Learn by doing.

Cheaper to stack 100 LIGO's ;), funny thing the estimated budget for a 10x (long) LIGO is about 100x. Dr. Weiss told me that was probably not going to happen.
 
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But you can bootstrap away the capacitance. The source follows the gate because of the feedback; that would be even more precise in a real follower.
Also, one can make the drain follow the gate by kicking the base of the cascode, so
there is no capacitive current between G and D.

Have you explored using depletion mode mosfets for the cascode? In my experience they work very well and simplify the circuits a lot. For 250 mA they may be a very good fit. In sims and testing I have not seen an impact on noise even with the IF3602.
 
Have you explored using depletion mode mosfets for the cascode? In my experience they work very well and simplify the circuits a lot. For 250 mA they may be a very good fit. In sims and testing I have not seen an impact on noise even with the IF3602.

No, I use FZT869TA for the Cascode and FZT951TA for the current sources.
Both in SOT-223.

In Sim, I also saw no influence of the cascode on the noise; only very slightly
at > 200 mA and > 400 KHz with 8 IF3601; that could be improved by paralleling two
FZT869.

It was not worth to include into the layout.
 
I would like to simulate your circuit in MicroCap (my default simulator) - would you post your schematic or maybe the LTspice file (I can then manually create the design in MicroCap)?





30u foil/66Meg input coupling, common source FET stage, 50...100 mOhm in sources
for feedback. NPN cascode, active load. Transimpedance stage with ada4898, fb taken
from here, gain = 60 dB to this point. I could not get it stable with 50 dB.

The many FETs pose a input cap. problem. Cgs is largely removed by the feedback to
the sources.

Cgd Miller does not apply because of Cascode, TIA cannot do that alone.
The base of the Cascode-NPN gets a level-shifted version of the input signal,
so the AC across Cgd is zero. (Bootstrap)

There is an integrator to generate the negative gate voltage. A window comparator
checks if we are close to the chosen operating point. If we are not, the gate resistor
is reduced from 66 to 4.7 Meg to speed up settling.

That would otherwise take forever. Lower corner of the passband is 0.1 Hz, goes
up to 1, maybe 2 MHz.

1/f corner is 30 Hz for IF3602, 1KHz for BF862. Some of the new FETs from
ON Semi may have a 40 Hz corner, have ordered them.

LTspice simulation says that 4 IF3602 pairs could reach 95 pV/rt Hz above 30 Hz;
That requires abt. 250 mA Id, not too excessive for 8 transistors.

The 50 mOhm source resistor is the largest noise contributor after the FETs, then the
cascode transistor and then the active load. Spice really helped through the
iterations to peel this onion.

Let's see how it works in reality.
 
From the existing threads, this is the one that fits best. Don't want to open yet another one.

I'm trying to select 4 somewhat similar IF3602 pairs. OMG! That will cost me some money. €420 for the 7 DUTs up to now. At a given Vgs, some will be completely off while others hog all the current. :mad:

Vgs from R&S NTG20, Vdd from HP6633B set to 4V, limited to 85.4 mA to protect the FET.
Note that I avoided to write matched pairs. >> 100mV offset is not matched in my book.
I wonder how single IF3601 would fare.


cheers, Gerhard
 

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