Better keep the trans-diodes matching the transistors. The gate resistors can be any value form 100ohm (what Joachim used I think) up to 10k (the highest value that I simulated). Values from 100 to 470ohm are practical values.
Joachim did the offset nulling by trimming R10/11 (I think). A practical solution will be, use 50ohm for R10 and R11, then place a 100ohm trimmer in-between and connect the input signal to the center-tab.
If you have a FFT-measurement solution, then the current sources can be used to trim for minimum THD (Joachim should have more information on this). When trimmed for minimum THD the buffer should be 'invisible' for most (if not all) measurement tools.
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I am a bit surprised that R10 / R11 are 100 Ohm in schematic 10100.
I my build i use 500 Ohm.
I trimed the offset in a different way.
M7, M8 have source resistors in my build ( actually i have a source resistor only in the source of M7 ).
With this source resistors you can trim away the Ugs difference in the output MosFets.
Mostly the source resistor will be in the N-channel.
The J113 have to be selected for the same Idss.
Fine trim is then done with one of the current sources ( J5, J6 ) dependent if the residual offset is positive or negative.
When the Ugs difference is trimmed well the least amount of offset also brings the least amount of distortion provided that semiconductors are well selected.
In my first build the minimum distortion did not correspond with the minimum offset.
Residual offset was 400mV. Not a problem in my system because my main amp is AC coupled. I later improved on that by better matching.
Although this design is not overly complex it is not a beginners project when you want the best result.
It is very transparent though. I hear things in the very deep bass i simply did not recognize before. Dynamics are tremendoes too.
It needs some time to run in. In the beginning it may sound a bit thin. That disappears after some use.
I my build i use 500 Ohm.
I trimed the offset in a different way.
M7, M8 have source resistors in my build ( actually i have a source resistor only in the source of M7 ).
With this source resistors you can trim away the Ugs difference in the output MosFets.
Mostly the source resistor will be in the N-channel.
The J113 have to be selected for the same Idss.
Fine trim is then done with one of the current sources ( J5, J6 ) dependent if the residual offset is positive or negative.
When the Ugs difference is trimmed well the least amount of offset also brings the least amount of distortion provided that semiconductors are well selected.
In my first build the minimum distortion did not correspond with the minimum offset.
Residual offset was 400mV. Not a problem in my system because my main amp is AC coupled. I later improved on that by better matching.
Although this design is not overly complex it is not a beginners project when you want the best result.
It is very transparent though. I hear things in the very deep bass i simply did not recognize before. Dynamics are tremendoes too.
It needs some time to run in. In the beginning it may sound a bit thin. That disappears after some use.
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The 500ohm value is from the original unity-gain version. The value of these can be manipulated to set the bias current in the output mosfet's.
Also, the source resistors are from the unity-gain version, when applied they will make for a slightly higher output resistance (as they are outside the feedback loop).
Yes, I think it was your question that made me recalculate it for the gain version
100 Ohm sets a output bias current of 4.5mA 200ohm sets 15mA and 500ohm sets 60mA (in simulation). This current is also strongly dependent on the current set in the current sources.
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why not make a servoed version where the drive currents are mirrored in (in place of the Jfets).. my gut says that when you have gain balance you also have 0 offset and lowest distortion. i don't have my simulator with me, but when home I'll play a little with the circuit concept.
cool with the bootstrap error correction.
This type of buffer with gain is ideal for preamps.
cool with the bootstrap error correction.
This type of buffer with gain is ideal for preamps.
Sofar the best ( most transparent ) line stage i heard.
Exceptional bass.
I think for lowest distortion the output Mosfets need to be the same transconductance after the Ugs trim.
The BJT´s should ideally be selected for Ube and Hfe.
Under this conditions the DC trim is also the min. distortion trim.
Not trimmed distortion figures where good too but 10dB worce as with the trim.
Exceptional bass.
I think for lowest distortion the output Mosfets need to be the same transconductance after the Ugs trim.
The BJT´s should ideally be selected for Ube and Hfe.
Under this conditions the DC trim is also the min. distortion trim.
Not trimmed distortion figures where good too but 10dB worce as with the trim.
Fairchild or OnSemi BC5xxC will typically be matched to within 300uV-1mV out of the box, which is extremely good and is more than enough to get repeatable operating points from the same batch of transistors.
AFAIK there is not much point in matching Vgs since the complimentary BJTs don't have matched Early effect.
One thing that might help though is to add an extra Cgs to the Mfet that needs it, to get the right value to cancel with the Cgs of the other Mfet. This has been effective for me in simulations.
AFAIK there is not much point in matching Vgs since the complimentary BJTs don't have matched Early effect.
One thing that might help though is to add an extra Cgs to the Mfet that needs it, to get the right value to cancel with the Cgs of the other Mfet. This has been effective for me in simulations.
The resistors won't contribute any detectable harmonic distortion unless the Mfets are oscillating. Since the gates in this circuit are essentially current-driven, the voltage across the resistors will be ignored, just like Vgs, which it will also be swamped by. The Ig however is the current the BJTs must drive, and in fact the source is driving the FETs by proxy through the BJTs. The Ig of the Mfets and the CCS leakage currents are greater distortion mechanisms than the gate stoppers by far.
Yes. However the ratio of Gm to Cgs is also important, since Gm determines the voltage swing across the capacitor. And even when the individual Gm of each Mfet is accounted for, the transfer curves may be different, so the harmonics won't cancel. So the best value of the cap can't really be predicted readily. If the Mfet with smaller Cgs has much lower Gm, then it would actually be the other Mfet that needs extra capacitance.
So really if you want be sure, you have to build the prototype and see if there is a distortion null using a trimcap. It could be that the CCS leakage swamps out any effect from Cgs, making all this pointless.
I would try the cap in simulation as proof of concept, to see whether or not it has a significant effect on the output. If not, I would determine the dominant distortion mechanisms in the circuit and work on the nails that stick out.
So really if you want be sure, you have to build the prototype and see if there is a distortion null using a trimcap. It could be that the CCS leakage swamps out any effect from Cgs, making all this pointless.
I would try the cap in simulation as proof of concept, to see whether or not it has a significant effect on the output. If not, I would determine the dominant distortion mechanisms in the circuit and work on the nails that stick out.
Except that Id for the N-channel will be Iq/2 while Id for the P-channel will be Iq/3. Because the FETs will have different Id, the transconductance will also be different, and probably still unmatched.