The Jfet/bootstrap combination CCS is unusual, but I think it is better in some ways than a BJT CCS. The MOSFET VAS is even more unusual, but according to reports, the specific device(s) chosen do their job exceedingly well. I think that it depends more on the skill of the designer.
- keantoken
- keantoken
oops.
The VAS current is essentially constant in the quiescent state.
The resistor drops an essentially constant voltage in the quiescent state.
That Vdrop is used to set the voltage sent to the gates of the two output FETs. Thus output bias current is set by adjusting 500r VR.
Andrew, you'll find there are two 500R pots, and Ontoaba was asking about R6.
In this schematic:
http://www.diyaudio.com/forums/soli...as-lateral-output-perfect-31.html#post2647498
- keantoken
In this schematic:
http://www.diyaudio.com/forums/soli...as-lateral-output-perfect-31.html#post2647498
- keantoken
Has someone the multisim model for DN2530? thanks.
The offset problem can be solved with a tracking opamp like I do, make a low pas filter so that it do not affect the audio Low Pass, 10 Hz of so.
I have in mij hybride amps also a opamp for this and sound is not effected but it keeps the valve so that I have no more then 100 uV - 1mV of offset and it do tracking valve aging.
Schematic and instruments in attachment, it is only a new test, so C10 is double but is not needed. I go test also schematic here, inplement vertical fets, if I am allowed afcourse..
The offset problem can be solved with a tracking opamp like I do, make a low pas filter so that it do not affect the audio Low Pass, 10 Hz of so.
I have in mij hybride amps also a opamp for this and sound is not effected but it keeps the valve so that I have no more then 100 uV - 1mV of offset and it do tracking valve aging.
Schematic and instruments in attachment, it is only a new test, so C10 is double but is not needed. I go test also schematic here, inplement vertical fets, if I am allowed afcourse..
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I use multisim it is easy to use, but a little buggy expecially the ultiboard part who is not so easy, but there exists a free pcb program here DesignSpark | The gateway to online resources and design support for engineers
I have downloaded supertex spice models but it gives errors in multisim, maybe someone here has a already made modelfile in his multisim for the DN2540.
I have downloaded supertex spice models but it gives errors in multisim, maybe someone here has a already made modelfile in his multisim for the DN2540.
Not exactly sure what CFA is but the general thrust of this thread in it's inception was the design of a mosfet amp that was as simple as can possibly be.
As it happens this i/p arrangement is not only simple it also significantly contributes to a design that can be used without any compensation and can sound very nice indeed.
mike
I use LTSpice and it has worked fine for most of what I do. However for simulating amplifiers it takes some setup to achieve best resolution and accuracy.
On that subject, I notice some of you are using my standard command set for simulating amplifiers. This version is flawed, I'm sorry to say. I looked at it again a while back trying to adapt it to be more flexible, and discovered this. The version below will give a lower noise floor. I am open to suggestions to add functionality for example automatic CCIR distortion, square wave, output impedance measurements and that sort of thing (though there are only so many things that can be done).
.options plotwinsize=0
.options method=gear
.options numdgt=7
.param Freq=1k
.param numcyc=10
.param dlycyc=5
.param FFT=2**16
.param simtime=numcyc/Freq+dlytime
.param dlytime=dlycyc/Freq
.param timestep=(simtime-dlytime)/FFT
.four {Freq} V(Vin) V(Vout)
.four {Freq} 4 V(Vin) V(Vout)
.tran 0 {simtime} {dlytime} {timestep}
;ac dec 1k 1m 1G
The 2**16 simply means 2^16 in LTSpice terms. This is easier than specifying the number of FFT points with the full number. This way, just use 2**15 or 2**17 to change the data resolution. This way the number of samples will always match the FFT samples taken which gives the lowest noise floor. 2**16=65536 which tends to be optimal, but you raise this if your computer is fast so you have better default resolution.
- keantoken
On that subject, I notice some of you are using my standard command set for simulating amplifiers. This version is flawed, I'm sorry to say. I looked at it again a while back trying to adapt it to be more flexible, and discovered this. The version below will give a lower noise floor. I am open to suggestions to add functionality for example automatic CCIR distortion, square wave, output impedance measurements and that sort of thing (though there are only so many things that can be done).
.options plotwinsize=0
.options method=gear
.options numdgt=7
.param Freq=1k
.param numcyc=10
.param dlycyc=5
.param FFT=2**16
.param simtime=numcyc/Freq+dlytime
.param dlytime=dlycyc/Freq
.param timestep=(simtime-dlytime)/FFT
.four {Freq} V(Vin) V(Vout)
.four {Freq} 4 V(Vin) V(Vout)
.tran 0 {simtime} {dlytime} {timestep}
;ac dec 1k 1m 1G
The 2**16 simply means 2^16 in LTSpice terms. This is easier than specifying the number of FFT points with the full number. This way, just use 2**15 or 2**17 to change the data resolution. This way the number of samples will always match the FFT samples taken which gives the lowest noise floor. 2**16=65536 which tends to be optimal, but you raise this if your computer is fast so you have better default resolution.
- keantoken
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