Hi,
You may take a look at this thread, preamp-buffers-simple-idea
I wouldn´t recommend the SK170 as JFETs, as they are quite expensive nowadays with considerable risc of sourcing fake parts and due to my latest experiences with the LSK389C replacements from LinearSystems and the BF246.
All JFETs suffer from Gate leakage, which means that a small current leaks from or into the Gate, similar to the base current of bipolars.
In comparison the Gate leakage is so small that it typcally doesn´t play a role in the design of a circuit.
But - and that´s a BIG BUT- under certain -and quite common(!)- circumstances Gate leakage ´explodes´.
This circumstances are high Temperature, high drain current and high drain-source voltages.
All three parameters unite in the simple JFET-Buffer, as the buffer is often biased at Idss or just below Idss, with Vds mostly greater than 10V and accordingly high temperature due to high heat power losses.
Unfortunately Gate leakage diagrams are not often printed in Datasheets or under totally unrealistic conditions.
Now what happens is, that if gate leakage reaches a certain value it leads to an increase in gate-source voltage, which in turn leads to higher drain current and temperature, which in turn raises gate leakage further.
A self-amplifying process called latch up occurs from which the device doesn´t recover but will be destroyed.
As a rule of thumb, Gate leakage stats from ~1/4 Vds max.
So a JFET specced for 40V of drain-source voltage may exhibit gate leakage from ~10V on.
Devices like the BF246 but also the 2SK170/LSK170 (and their Duals) are sensitive with regard to gate leakage.
The afore mentioned JFETs 4393, 4392 and 4391 are less sensitive, are lownoise devices and much cheaper devices and are still produced by a couple of manufacturers.
In the linked thread You´ll notice that the JFETs all feature source resistors.
This keeps the dain current lower than Idss and reduces tolerance sensitivity of the JFETs.
A measurement to allow for the use of gate leakage sensitive devices is to cascode them as it´s done in circuit B of the link.
A circuit that never failed, while with circuit A I had quite a number of them failing.
The cascoding also improves THD figures alot and reduces the heat power losses of each device.
While the simple Buffer may not be better than -40dB to -60dB THD circuit B may improve THD by 20dB and more.
Besides more parts the only drawback is that the gate-source voltage of the cascoding JFET subtracts from the maximal signal voltage.
Supplied from 30V or +-15V the clipping point is still sufficiently high, well above 5Vrms.
With the combination of SK170/4391 or 4393/4391 the lower JFET´s drain-source voltage is held quite constant at ~4V, far safe off of gate leakage.
A worthwhile tweak of the simple circuit A.
Wiki shows the topology of unity gain Sallen-Key Filters.
Just replace the OPAmp symbol by a Buffer stage (gain=1) like circuit A or B and You notice Andrew´s sketch.
A final remark.
The simple JFET-Buffers work in class A mode only.
The maximum current into a attached load equals the bias current.
But if THD shall remain low the load current should not be larger than 1/10 to 1/5 the bias current value.
In other words You require high ohmic loads greater than 5-10kOhms
See that the combined load of load impedance and the filter´s impedance that is presented to the buffer output remains high enough.
In case You need more current capability You could beef up circuit A and B to circuit C.
It is just an add-on to those topologies using two bipolar PNPs and a couple of lowcost passive devices.
It easily allows for 10x the load current and much lower load impedances.
jauu
Calvin
You may take a look at this thread, preamp-buffers-simple-idea
I wouldn´t recommend the SK170 as JFETs, as they are quite expensive nowadays with considerable risc of sourcing fake parts and due to my latest experiences with the LSK389C replacements from LinearSystems and the BF246.
All JFETs suffer from Gate leakage, which means that a small current leaks from or into the Gate, similar to the base current of bipolars.
In comparison the Gate leakage is so small that it typcally doesn´t play a role in the design of a circuit.
But - and that´s a BIG BUT- under certain -and quite common(!)- circumstances Gate leakage ´explodes´.
This circumstances are high Temperature, high drain current and high drain-source voltages.
All three parameters unite in the simple JFET-Buffer, as the buffer is often biased at Idss or just below Idss, with Vds mostly greater than 10V and accordingly high temperature due to high heat power losses.
Unfortunately Gate leakage diagrams are not often printed in Datasheets or under totally unrealistic conditions.
Now what happens is, that if gate leakage reaches a certain value it leads to an increase in gate-source voltage, which in turn leads to higher drain current and temperature, which in turn raises gate leakage further.
A self-amplifying process called latch up occurs from which the device doesn´t recover but will be destroyed.
As a rule of thumb, Gate leakage stats from ~1/4 Vds max.
So a JFET specced for 40V of drain-source voltage may exhibit gate leakage from ~10V on.
Devices like the BF246 but also the 2SK170/LSK170 (and their Duals) are sensitive with regard to gate leakage.
The afore mentioned JFETs 4393, 4392 and 4391 are less sensitive, are lownoise devices and much cheaper devices and are still produced by a couple of manufacturers.
In the linked thread You´ll notice that the JFETs all feature source resistors.
This keeps the dain current lower than Idss and reduces tolerance sensitivity of the JFETs.
A measurement to allow for the use of gate leakage sensitive devices is to cascode them as it´s done in circuit B of the link.
A circuit that never failed, while with circuit A I had quite a number of them failing.
The cascoding also improves THD figures alot and reduces the heat power losses of each device.
While the simple Buffer may not be better than -40dB to -60dB THD circuit B may improve THD by 20dB and more.
Besides more parts the only drawback is that the gate-source voltage of the cascoding JFET subtracts from the maximal signal voltage.
Supplied from 30V or +-15V the clipping point is still sufficiently high, well above 5Vrms.
With the combination of SK170/4391 or 4393/4391 the lower JFET´s drain-source voltage is held quite constant at ~4V, far safe off of gate leakage.
A worthwhile tweak of the simple circuit A.
Wiki shows the topology of unity gain Sallen-Key Filters.
Just replace the OPAmp symbol by a Buffer stage (gain=1) like circuit A or B and You notice Andrew´s sketch.
A final remark.
The simple JFET-Buffers work in class A mode only.
The maximum current into a attached load equals the bias current.
But if THD shall remain low the load current should not be larger than 1/10 to 1/5 the bias current value.
In other words You require high ohmic loads greater than 5-10kOhms
See that the combined load of load impedance and the filter´s impedance that is presented to the buffer output remains high enough.
In case You need more current capability You could beef up circuit A and B to circuit C.
It is just an add-on to those topologies using two bipolar PNPs and a couple of lowcost passive devices.
It easily allows for 10x the load current and much lower load impedances.
jauu
Calvin
You suck up so much information !
Calvin is correct. Read all that again and again and again.
Now go and measure the Vdrop on the 1k0 gate resistor to see if heat and/or voltage is resulting in gate leakage current.
There is one part missing in Calvin's explanation.
+ve gate bias leads to gate leakage.
A jFET is usually operated with -ve gate bias and this is usually enough to avoid gate leakage, when Pq is kept to appropriate values.
A B1 with the device operating at Id = Idss, then the jFET spends roughly 50% of it's time in passing signal where +ve gate bias is applied. However, the B1 operates with 18Vdc and bl grade resulting in Pq ~54mW to 108mW
Gate leakage did not concern Pass in offering his circuit to the Community.
Calvin is correct. Read all that again and again and again.
Now go and measure the Vdrop on the 1k0 gate resistor to see if heat and/or voltage is resulting in gate leakage current.
There is one part missing in Calvin's explanation.
+ve gate bias leads to gate leakage.
A jFET is usually operated with -ve gate bias and this is usually enough to avoid gate leakage, when Pq is kept to appropriate values.
A B1 with the device operating at Id = Idss, then the jFET spends roughly 50% of it's time in passing signal where +ve gate bias is applied. However, the B1 operates with 18Vdc and bl grade resulting in Pq ~54mW to 108mW
Gate leakage did not concern Pass in offering his circuit to the Community.
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Hi,
yes You may place pots at that position as their input impedance is constant.
A log type is preferrable.
Standard values are 10k, 20k, 50k.
The lower value is preferrable noisewise, but keep the current capability of the Filter-buffer in mind.
As the pots are just required once for setup You may think of replacing them by a resistive voltage divider later.
jauu
Calvin
yes You may place pots at that position as their input impedance is constant.
A log type is preferrable.
Standard values are 10k, 20k, 50k.
The lower value is preferrable noisewise, but keep the current capability of the Filter-buffer in mind.
As the pots are just required once for setup You may think of replacing them by a resistive voltage divider later.
jauu
Calvin
Hi,
Andrew and I are talking of slightly different effects.
The Gate-Source path of a JFET forms a Diode - which is similar to the Base-Emitter-Path of a bipolar.
A positive Vgs brings this Diode into conduction, the same as a Bipolar opens up with sufficient Vbe.
The JFET then conducts higher than Idss currents.
As long as power and heat limits are not exceeded this may be done so.
Its not recommended though because the allowed positive range is quite small and gate current starts flowing, which in other words means that the input impedance drops.
Especially with filter circuits You wouldn´t want that impedance to vary all over the place for 50% of Your signal time.
Beeing a normally open (depletion mode) device the JFET opens up if its Vgs is becoming negative.
Then the gate-Source-Diode is reverse biased and cut off.
Still though a tiny current leaks out, the gate leakage, which is a unwanted stray effect (of every Diode).
But contrary to the biasing current which actually sinks slightly with temperature, the leakage currents rise exponentially with temperature (roughly doubling every 10° rise).
The second effect is called impact ionization and it occurs with increased drain-source voltages.
IIrc the Pass B1 is supplied with 18V, meaning that at idle the Vds of each JFET is 9V.
The SK170´s Gate-Drain breakdown voltage is specced at 40V, hence below the range of impact ionization (1/4 BVgss).
With a supply of 24V to 30V each JFET would see 12V or more at idle, finding itself already in the range of impact ionization.
I´d strongly suggest to at least reduce Id with source resistors or to cascode the JFETs und er these conditions.
jauu
Calvin
Andrew and I are talking of slightly different effects.
The Gate-Source path of a JFET forms a Diode - which is similar to the Base-Emitter-Path of a bipolar.
A positive Vgs brings this Diode into conduction, the same as a Bipolar opens up with sufficient Vbe.
The JFET then conducts higher than Idss currents.
As long as power and heat limits are not exceeded this may be done so.
Its not recommended though because the allowed positive range is quite small and gate current starts flowing, which in other words means that the input impedance drops.
Especially with filter circuits You wouldn´t want that impedance to vary all over the place for 50% of Your signal time.
Beeing a normally open (depletion mode) device the JFET opens up if its Vgs is becoming negative.
Then the gate-Source-Diode is reverse biased and cut off.
Still though a tiny current leaks out, the gate leakage, which is a unwanted stray effect (of every Diode).
But contrary to the biasing current which actually sinks slightly with temperature, the leakage currents rise exponentially with temperature (roughly doubling every 10° rise).
The second effect is called impact ionization and it occurs with increased drain-source voltages.
IIrc the Pass B1 is supplied with 18V, meaning that at idle the Vds of each JFET is 9V.
The SK170´s Gate-Drain breakdown voltage is specced at 40V, hence below the range of impact ionization (1/4 BVgss).
With a supply of 24V to 30V each JFET would see 12V or more at idle, finding itself already in the range of impact ionization.
I´d strongly suggest to at least reduce Id with source resistors or to cascode the JFETs und er these conditions.
jauu
Calvin
The 20.5 dBs amp is class A/B 100W rated & the 26 dBs amp is class A 75W rated, 1st attempt will be 2 way so have I to use the more dBs for the mid-bass or to use the more watts? how to calculate the attenuation necessary to have the same gain in both ways: the tweeter have 89 dbS @ 6 ohms & the woofer have 88 dBs @ 8 ohms?
Why two input buffers?
Thanks
Pardon my ignorance, but why do you have an input buffer for both the HP and LP sections? On the assumption that the XO will follow a volume control (and perhaps other things), I can see why you need a buffer, but why not one buffer feeding both the HP and LP sections? Certainly if the thing preceeding it is a Vol control, a dual is much easier to source than a quad. The op amp ones I have seen (e.g. Rod Elliot's) use only one buffer with both sections attached to it.
Thanks
OK, the basic assumption is that the LF/HF inputs of the active filter will be fed with a stacked pot of some unspecified resistance from the output of whatever preamp the builder happens to have/make.
Within reason, you want a reasonably high resistance pot in each case so as not to load down the signal source.
At the same time, the driving impedance to each filter must be low, as the driving impedance otherwise insinuates itself into the transfer function of the filter, whether it be LP or HP (more obvious in the case of LP, as there's an actual resistor at the input).
If you use a follower at each input, all these considerations melt away - comprende?
Within reason, you want a reasonably high resistance pot in each case so as not to load down the signal source.
At the same time, the driving impedance to each filter must be low, as the driving impedance otherwise insinuates itself into the transfer function of the filter, whether it be LP or HP (more obvious in the case of LP, as there's an actual resistor at the input).
If you use a follower at each input, all these considerations melt away - comprende?
This is superficially true, but there are different sources of bias for both LP and HP filters on a different channel - please propose a different solution that sorts all the issues out and post it here for our elucidation. It's not many more components for separate buffers, and no issues otherwise.
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