Help with Class D Amplfier Design (feedback)

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Tekko,

I used strands of nichrome wire twisted together, its good because it can withstand high temps pretty well, and has a fairly high resistance / meter.



Tiki,
Yes That is wood, however the wire should never get too close, the only way it will is if i pump the amp too hard, the wire will break and drop. ( i know from experience). I keep overloading the dummy load. By the way if you think thats scary, you should see my 2 ohm load when being pumped hard!!!!!.

I can post the final artwork photos of the pcb, and schematic if you want.


Pierre,
At the moment I am using the self-osc setup, each channel is running at 230kHz, i not having any problems of the so called whisting etc you said would probably be a problem. After making up the proper pcb's, ie not my prototype one. The output frequency is very constant with varying power levels, unlike the prototype.

I am planning on getting some measurements soon, I've just been having too much fun pumping kw's into big speakers. Let me tell you geeeeeeeee does this thing pump out some bass!!!!!!!!!!!...


Thanks to everyone that has replied!


Regards

Peter
 
I just did some test on the amp (one channel of it anyway) with RMAA,

This is what its come up with. I don't know what exact power level it was at but i can confirm that my 4 ohm dummy load was glowing red thought bits of the test.


Freq Response dB: +3.07,-0.73
Noise Level dBA: -56.6
Dynamic Range dBA: 54.8
THD %: 0.208
Intermodulation %: 1.6 *
IMD Swept Freq %: 2.1 *

The freq response is really quite flat, its within +/-0.5dB up until about 10kHz where it starts to rise a bit, thats where the +3.07 is coming from. It rises up to about +5dB at 20kHz. Hmmmmm I think it must be my filter starting to resonate!! but i am not sure.

The two i have marked with a `*' i beleive are actually caused by the soundcard in this computer, as on the loop back they are 2.6 and 15.13% respectively!!! with is real bad. However off my laptop these figures are much much smaller, however my laptop doesn't have a line in, just mic in so its much more prone to noise.

Regards

Peter.
 
Peter, have you tested the PWM waveform (you show it in a picture in this thread) WITH load and input? It is difficult to sync as its duty cycle varies (it should :) ), but at least you can check for overshoot or undershoot of the signal. I experiment this in my prototype, about 20V of undershoot in the negative phase of the signal, but only at high/low duty cycles, when a lot of power is being pushed. When idle I get a 50% duty cycle perfect square wave, however.

This could compromise reliability.

Could you check that?

Best regards,
Pierre
 
Pierre,

I am not quite sure at what you are talking about, I have triggered my Scope on the input waveform and watched the output, I havn't noticed any significant over-shoot.

I am still trying to get my overcurrent tripping to work faster, I am getting sick of killing FETS. I've tried all different schemes.


I'll Be happy when i get that bit working.

Regards

Peter
 
Hello, Peter.
I look at it by watching at the PWM waveform at the mosfets output, then input a sine wave up to full power. In the oscilloscope you obviosly see the waveform moving due to the modulation, but you can see if there is something going up or down the rails due to peaking in the switching.

About the protection: have you seen last posts in the "mosfet reliability..." thread? Subwo1 suggested a Rds(on) based current measurement. You can trigger a timer that turns outputs off for a while. If you do it fast (using a logic gate or the like) it can work better than the resistor sensing (apart from having higher efficiency and lower output impedance).


Best regards
Pierre
 
Hi Pierre,

I will hook up everything tomorrow and do that test as you described to see what i can find.

As for the current protection, I like the look of subwo1's idea, however i am not sure how that will go if the short happens while the high side mosfet is running.

Currently I am using a current sense resistor on the ground return from the speaker, I use two opamps one set up as an inverting and other set up as a non-inverting amplifers, i feed the outpu of thise though two signal diodes, which inturn pulls a latch high. It works perfectly except that if i short it at a high power level the mosfets die :(

Anything below 50% and its fine, i just have to press the reset button to release the latch.

I really want to make this amplifier protected from a short of any kind, because the application it needs to be durable.

Regards

Peter
 
hypnopete said:
As for the current protection, I like the look of subwo1's idea, however i am not sure how that will go if the short happens while the high side mosfet is running

What didn't occur to me is that it may work for me because the MOSFETs are capacitor coupled to the output transformer. Also the duty cycle never goes higher than 50%.

In class D audio, the inductance of the output choke should protect the upper MOSFET for a half cycle so long as the duty cycle does not cross a certain threshold. Consider that the output inductor is already dropping about 95-98% of the voltage during each half-cycle. The output filter capacitor is practically seen as an AC short by the MOSFETs. Each half cycle, the capacitor voltage rises maybe 2v, except when the output goes more than about 2/3 up.

So in the case of the slow opamp response and the half-cycle protection coming up short during high power output, it may work to do as Peter has done, but use two high speed comparators instead. Best Regards.
 
It should so long as the duty cycle is below a certain point determined by the trigger point of the circuit--the sensitivity. Between, for example, +70 and -99% duty cycle, it could offer protection.

I am trying to think of a floating protector for the upper MOSFET. It seems it could be done like the lower one if a gate of a floating Schmitt trigger CD40106 were to turn on the diode of a 6N137 high speed optocoupler. The output of the optocoupler would then instantly latch protection.
 
Subwo1,

I think i will try using a couple of high speed comparators as you suggest, As i said I do like your idea about sensing the voltage drop across the Vds, but unfortuantly it seems like it will get quite complicated to also sense across the upper side fet, I agree I believe that the Capacitor coupling will definatly help the survivablity of the mosfets.

Currently I have just been using a TL-072 as my sensing op-amp, maybe i should just try a faster op-amp? I don't know if i would like to use just a comparator, as the resulting sense signals are already very small, and this could make the high-speed comparators prone to false triggering from noise etc.


Regards

Peter
 
Hi Peter, I was thinking the faster opamp idea too. But the same reason why the output inductor can protect the MOSFETs a cycle or so is why detecting overload after the inductor may be a bit slow.

There is a possibility that one NPN and one PNP transistor could send an overload indication down to the lower rail where it could trigger the shutdown pin. It could be iffy because the switching transients may tend to trigger falsely. Basically, the gate drive feeds the NPN base. The emitter connects to the source. The base-emitter junction of the PNP connects between the collector and the upper MOSFET drain. Suitable resistors are inserted where needed.
 
I agree with subwo1 in that sensing at the speaker return will be slow to protect the mosfets totally.
About Peter's idea about changing to a faster opamp, I think it is easier and more fast to use comparators (LM319 is fast enough IMHO and cheap), and to prevent false triggering due to the small signal, you can add a little of hysteresis.
Another possibility is to level shift the sense signal to, say, half-vcc-1V when no load, and feed it to a logic gate with hysteresis, as 74HC14.

Best regards,
Pierre
 
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