roender,
I`ve taken a look at the input stage of your amp. In my opinion, the JFETs are not used in their most linear region. Both Ids and Vds are excessive, I would call it an abuse, no wonder you find them susceptible to thermal distortion. The voltage reference is a high impedance (10kOhm) resistor.
I`ve taken a look at the input stage of your amp. In my opinion, the JFETs are not used in their most linear region. Both Ids and Vds are excessive, I would call it an abuse, no wonder you find them susceptible to thermal distortion. The voltage reference is a high impedance (10kOhm) resistor.
Lumba Ogir said:
Yes, your are correct ... my amp is trash.
I thought we are talking about thermal distortion in j-fet based CCSs, not in input stages ...
Also, 2sk170 present more and more thermal coefficient if the current decrease through them. It has zero TC at around 13mA.
And for your information, the folded cascode topologies relays in input stage gain only, and in the case of k170 based input stage, the more current the more transconductance we get from them, not to mention the sound of a highly biased j-fet.
All the factory (Toshiba) measurements, including noise, are made at 10Vds ... why?
roender,
I have not said that, on the contrary.
We are talking about the same thing. I`m trying to find out the cause of the problem by looking at your circuit.
An absurd supposition. Thermal coefficient has no relevance whatsoever here. Almost all parameters are temperature-dependent, a temperature increase does not improve any of them.
Another misconception. The gain is mainly provided by the cascoding transistors, the FETs should not have high gain, which is one of the purposes of cascoding. (They will not have high gain anyway because of the very low output impedance, set by the cascoding transistors).
Manufacturers present the specifications as they please, but specifications don`t by any means imply a recommendation for usage. That`s the designer`s job.
Lumba,
This conversation led to nothing or maybe you will learn something after all:
1. All j-fets have a sweet spot where thermal coefficient is ZERO, where Ids or/and Vgs don't change with temperature.
2. A cascode device, bjt or fet, is in common base topology and has ZERO gain.
3. In folded cascode amplifier topologies, the gain is provided by the input stage only.
Did you ever read this paper?
http://www.borbelyaudio.com/adobe/ae599bor.pdf
http://www.borbelyaudio.com/adobe/ae699bor.pdf
Regarding J-fet thermal behavior:
"The change in the transconductance
curve is not just a matter of tolerances
due to manufacturing, but it also depends
on the temperature, and this is
due to two different effects. As the temperature
increases, the mobility of the
charge carriers in the channel decreases,
which leads to an increasing channel resistance,
and hence a reduction in ID.
On the other hand, the barrier potential
of the gate pn junction decreases
about 2.2mV/°C, which causes the ID to
increase. There is a point on the
transconductance curve where these
two effects cancel one another, and the
temperature coefficient (tempco) becomes
zero. Obviously, if you need to design
for low drift, then the JFET must be
operated at this point.
You can calculate the zero tempco
point with the following formula:
VGS = VP + 0.63V
Typical transconductance curves for two
different JFETs are shown in Figs. 3A and
3B for a high-VP and a low-VP JFET, respectively.
It is obvious from the curves
that the zero tempco point occurs at a
lower ID for high-VP JFETs and at a higher
ID for low-VP JFETs. If the VP is close to
0.6V, then the zero tempco point is close
to IDSS. "
This conversation led to nothing or maybe you will learn something after all:
1. All j-fets have a sweet spot where thermal coefficient is ZERO, where Ids or/and Vgs don't change with temperature.
2. A cascode device, bjt or fet, is in common base topology and has ZERO gain.
3. In folded cascode amplifier topologies, the gain is provided by the input stage only.
Did you ever read this paper?
http://www.borbelyaudio.com/adobe/ae599bor.pdf
http://www.borbelyaudio.com/adobe/ae699bor.pdf
Regarding J-fet thermal behavior:
"The change in the transconductance
curve is not just a matter of tolerances
due to manufacturing, but it also depends
on the temperature, and this is
due to two different effects. As the temperature
increases, the mobility of the
charge carriers in the channel decreases,
which leads to an increasing channel resistance,
and hence a reduction in ID.
On the other hand, the barrier potential
of the gate pn junction decreases
about 2.2mV/°C, which causes the ID to
increase. There is a point on the
transconductance curve where these
two effects cancel one another, and the
temperature coefficient (tempco) becomes
zero. Obviously, if you need to design
for low drift, then the JFET must be
operated at this point.
You can calculate the zero tempco
point with the following formula:
VGS = VP + 0.63V
Typical transconductance curves for two
different JFETs are shown in Figs. 3A and
3B for a high-VP and a low-VP JFET, respectively.
It is obvious from the curves
that the zero tempco point occurs at a
lower ID for high-VP JFETs and at a higher
ID for low-VP JFETs. If the VP is close to
0.6V, then the zero tempco point is close
to IDSS. "
If my understanding of the cascode is right, you both might be wrong. I always thought, that the lower transistor, the fet in roender's case, provides current gain, but has no voltage gain, which is taken over from the upper device. So there are no changing (with gain) spurious capacitances, or in fact much lower, so the miller efffect is damped. In my books, a common base transistor does indeed have voltage gain, but provides no (additional) current.
Rüdiger
Rüdiger
roender,
-2.2mV/°C is the temperature coefficient of a P-N junction (as opposed to the MOSFET`s positive 0.7%/°C to 1%/°C). Good to know but...the idea of choosing Iref solely on the bases of that does not make me excited at all. There are some other parameters of crucial interest for linearity and more effective methods to stabilize them especially under harsh dynamic conditions. (The Proportional to Absolute Temperature Approach is a very tricky business).
May I humbly propose a thorough operational review of the cascode and CFP compounds, you might find it much more complex than immediately appears.
Hannes,
right?
By the way, have you ever fixed that amp?
-2.2mV/°C is the temperature coefficient of a P-N junction (as opposed to the MOSFET`s positive 0.7%/°C to 1%/°C). Good to know but...the idea of choosing Iref solely on the bases of that does not make me excited at all. There are some other parameters of crucial interest for linearity and more effective methods to stabilize them especially under harsh dynamic conditions. (The Proportional to Absolute Temperature Approach is a very tricky business).
May I humbly propose a thorough operational review of the cascode and CFP compounds, you might find it much more complex than immediately appears.
Hannes,
right?
By the way, have you ever fixed that amp?
Lumba,
J-fets are much more linear close to Idss, from noise and forward transfer admittance POV. Of course is hard for them to be operated at such high Ids, especially when high Vds is required.
In my amplifier, the power dissipation is around 65mW ... did you see this as a potential problem?
I know how complex they are, but is of topic here
Cheers,
M
J-fets are much more linear close to Idss, from noise and forward transfer admittance POV. Of course is hard for them to be operated at such high Ids, especially when high Vds is required.
In my amplifier, the power dissipation is around 65mW ... did you see this as a potential problem?
Lumba Ogir said:
I know how complex they are, but is of topic here
Cheers,
M
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