diyAB Amp - The "Honey Badger"

What other way did you have in mind ? Servo ?

that would yet be another option, something i try to avoid...but that is just me...

your circuit has a small ccs feeding tail current,, and a big CCS feeding the VAS, here you can make adjustments in small increments, try changing the value of the emitter resistor until you nail that output offset voltage.....

fix those emitter degeneration resistors, get rid of that variable pot, 220 ohms is a good value, but anywhere from 47 ohm to 470 ohm can be used...
those resistors will be very small compared to the output impedance of the current mirrors to matter...

also, when using variable pots like that in the small ccs, it is better to use them in series rather than parallel, reason is you may turn it to its lowest
resistance and you will surely have problems...
 
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the Nch currents should add up to exactly the same as the Pch currents.
But they don't. You have an apparent 412mA Pch and 397mA, error ~3.8%

Did you select your source resistors to better than 1% (±0.5%)
All your measurments so far do not explain the 0.3V output offset error.

Are the input transistors passing the same drain current?
What is the Vdiff across the two source nodes?
What is the Vdiff across the two gate nodes? Measure to the outside of the gate resistors. Measuring directly to the gates may cause oscillation.
Agh !, there are no gate resistors !. Monitor the output with a scope to check as you touch the gates with a probe.

Vdiff across two source nodes is null (both source resistors pass 4mA)
Input gate is at 0 volts and inverting input gate is at 0.3v

Vdiff across Rin is nul
 
Rcruz,

referring to the schematics shown in #1644: Why are the bottom ends of C8 and R13 tied to the LTP's CCS, instead of ground?

Best regards!


Because referring to the common point of the LTP is better way to reduce the nonlinear capacitance of the LTP. Check out the original design of the HB:
280625d1336179640-diyab-amp-honey-badger-diya_classab_schematic.gif

Sajti
 
..referring to the LTP's common point means, that the common base of the cascode stage will be modulated by the common mode voltage of the LTP. It reduce the change of the Vds, and Vdg voltage of the input FETs.

The LTP's common point shows an AC voltage with half the level of the input signal and in-phase with the input. Thus, coupled by C8 Miller effect will be reduced for the positive input device. Seen by the negative device, the common point AC is out of phase, thus it's Miller effect is increased. Is this the point that leads to better performance?

Best regards!
 
The LTP's common point shows an AC voltage with half the level of the input signal and in-phase with the input.

This is true for the simple LTP circuit. But if You apply NFB it will reduce the difference between the input voltage and the voltage on the common point.
The HB use heavy feedback (over 20dB), so the AC voltage on the common point will be same as the input (and feedback) signal.

Seen by the negative device, the common point AC is out of phase, thus it's Miller effect is increased.

The phase of the feedback signal must be same, if You apply nfb.

Sajti
 
This is true for the simple LTP circuit. But if You apply NFB it will reduce the difference between the input voltage and the voltage on the common point.
The HB use heavy feedback (over 20dB), so the AC voltage on the common point will be same as the input (and feedback) signal.
Thanks for pointing this out, Sajiti! I must have to admit that I had overlooked this fact that a modern SS power amp has in common with a high OL gain opamp.

The phase of the feedback signal must be same, if You apply nfb.
This is true. My reflections two postings above referred to the positive input signal only.

Now I have to re-think: If the signals at both + and - inputs are the same and in-phase, the common point AC level roughly also is the same and in-phase with both. Same with both cascode transistors' bases, thus same with both input transistors' collectors, thus roughly constant Vce for both, thus improved linearity. Bingo!

Best regards!
 
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Vdiff across two source nodes is null (both source resistors pass 4mA)
Input gate is at 0 volts and inverting input gate is at 0.3v

Vdiff across Rin is nul
draw out your LTP+source resistors, with the two voltages @ +IN & -IN.
Measure the Vgs of both halves.
Mark that on your sketch.
Measure the Vdrop across each Source resistor.
Mark that on your sketch.

Does that all add up?

BTW,
The k170 datasheet shows ~180mVgs for a 6.2mA Idss device operating @ 2mA.
What should your Vgs be for your devices at your currents?
 
I been wanting to buy and build the honey badger for a long time now but whenever I look for it at diyAudio store it's never available.
Does anyone know if it's ever going to come back or have I just been unlucky when checking the website?

/Ejje

I surely hope they will be back in the diyAudio store. If not, I am sure someone will step in and make some boards.