Yes it did! 
And we are still waiting on our own Class-D section on www.diyaudio.com .........
Jan-Peter
www.hypex.nl
And we are still waiting on our own Class-D section on www.diyaudio.com .........
Jan-Peter
www.hypex.nl
Bricolo said:can I please see a "correct" schematic, to play with my simulator
You can try the one I gave you, it's nto perfect but you'll get it working.
I'm not saying Charles' won't work I'm just not sure how it does, it seems like yours is working but output is inverse, have you tried anything over 100mA? That's about the threshhold for my simulation so far (not good huh). Try a 1 volt input, than you'll know exactly your gain is just by the output. Also can't tell where you took the output from, I guess right at the load? Check what sort of crazy waves you have right before the filter inductor.
Don't worry if you don't get a nice working sim in a day, mine took alot of work/time. We'll keep the simulationable circuit as a goal (If no one disagrees) it wont' happen in a day but we'll get something good happening soon.
If you want to make the output stage easier to play around with just avoid the bootstrap circuit, (diode+cap) and add an extra Vdc source from the upper gate drive power rail to the source of the Fet it's driving. Then you'll just have the transistor switches to worry about working first.
Just work through it man it's the beauty of spice, does the comparator compare? How do those same comparator output waves look past the driver, OK? (the upper gate drive has to switch from rail to rail + at least 12V, lower driver output signal is just 0 to 12V or so with respect to the negative rail) All part of the fun of driving two N channels in a half bridge.
If they are OK, then check how the driver signals intersect each other ie: /\ or X or \/ in order from "it's going to explode" to ....better but not good.....to....done properly. To clarify what I'm trying to say there, the / portion is the ON signal of one and the \ being the off signal of the other. So you can see if they intersect like /\ They're both full turned on at the same time and that's a dead short across the rails. X lands intersection somewhere around Vth probably on the high side so it's still no good, while \/ ensures one mosfet is off before the other starts to turn on. In a perfect world, we'd have negative going gate signals as well, set up to intersect like X, where intersection lands right at 0V. Then you'd have something like 2.5 volts noise immunity on the drive signals. Neat stuff.
Scuse me for stating that if you already knew....but actually that'll be good info to have later on for someones first class D attempt.
How does the feedback signal look when mixed with the output?
Have you tried a bode plot? Might tip you off to other problems.
@IVX It sure did
What took you so long?Regards,
Chris
Jan-Peter said:Yes it did!
And we are still waiting on our own Class-D section on www.diyaudio.com .........
Jan-Peter
www.hypex.nl
Or take over this one! I noticed they have a new forum but it doesn't appear functional yet? Maybe they're still working out problems.
Regards,
Chris
Bricolo said:can I please see a "correct" schematic, to play with my simulator
Here is the first power comparator-type bridge output circuit I built for simulation almost a year ago. Note that the node labeled "M" stands for the junction between positive and negative power supplies which is also signal ground. I was unable to figure out how to get the digital-type Schmitt trigger chip to work otherwise since I had to make its power reference ground for the whole circuit. Also, state of the art DIY circuitry has advanced beyond this level and so have I. You can replace Q5, R11, D8 with a simple current source for simplicity, just play with its milliamp output to get the DC offset down at the outputs since the circuit does not have automatic output level zeroing.
I refrain from showing a later circuit because it is more complicated and still only but a simulated version. But, the thinking these days is to not include the 74C14 because it adds propagation delay, even worse, uneven for upper and lower switches too. Yet simulators like the circuit because it must oscillate due to the unequivocal output state of the 74C14.
Simulatable Class D Circuit
Chris:
Yes, I tested with more than 100mA
With a 4V RMS input, I see a 18V RMS output on the 6R load
The sine is thick, 1V pp oscillations on it
Yes, the output is inverted.
Before the inductor, looks like a working switching amp near rail to rail squarewaves
The comparator seems to work, the output is a variable duty cycle squarewave from -25 to -34V
But past the drivers the signals aren't oK
The upper fet's gate swings from +45 to -35
the mower fet's gate swings from -25 to +35, and seems to "saturate" when the output is at it's maximum or minimum
Can you show your schematic with a higher resolution, to see the values, please?
Yes, I tested with more than 100mA
With a 4V RMS input, I see a 18V RMS output on the 6R load
The sine is thick, 1V pp oscillations on it
Yes, the output is inverted.
Before the inductor, looks like a working switching amp
near rail to rail squarewavesThe comparator seems to work, the output is a variable duty cycle squarewave from -25 to -34V
But past the drivers the signals aren't oK
The upper fet's gate swings from +45 to -35
the mower fet's gate swings from -25 to +35, and seems to "saturate" when the output is at it's maximum or minimum
Can you show your schematic with a higher resolution, to see the values, please?
Attached is a small (partial) schematic, intended as a more concrete proposal to stir up some more discussion. (It's embarrassingly incomplete, actually 
. )
But it does have a first order loop filter (noise shaper), a comparator, output mosfets+filter, and the feedback.
There's a template for a comparator, which should read LT1016 in the picture! That's a very fast comparator; perhaps too fast for our immediate needs, but it has nice complementary outputs. It does require +/-5V (or just +5V/0V), so it's a bit of a hazzle in that way too. If anyone has a another suggestion, feel free to share it...
Whether the output from the op-amp goes to + or - of the comparator depends on whether the following output drive circuit is inverting or not.
Assuming it's OK to use dual positive/negative supplies (Vdd, Vss) with GND in between, the issue is how to drive the mosfet gates, with suitable amplification and level shifting of the comparator output(s).
Chris (classd4sure) suggested AC-coupled gate driving, which would imply using P/N-fets instead of two N-fets. That's actually how I myself have done it before - but I would be very happy to come up with another solution with only N-fets and no AC-coupling on the mosfet gates.
Perhaps using an IR211x-like driver circuit, but with AC-coupled level shifting between the comparator output and the driver circuit?
Or a discrete driver solution similar to the one in the UcD-patent (again with some level shifting needed)?
Or am I completely lost? You tell me!.
. )But it does have a first order loop filter (noise shaper), a comparator, output mosfets+filter, and the feedback.
There's a template for a comparator, which should read LT1016 in the picture! That's a very fast comparator; perhaps too fast for our immediate needs, but it has nice complementary outputs. It does require +/-5V (or just +5V/0V), so it's a bit of a hazzle in that way too. If anyone has a another suggestion, feel free to share it...
Whether the output from the op-amp goes to + or - of the comparator depends on whether the following output drive circuit is inverting or not.
Assuming it's OK to use dual positive/negative supplies (Vdd, Vss) with GND in between, the issue is how to drive the mosfet gates, with suitable amplification and level shifting of the comparator output(s).
Chris (classd4sure) suggested AC-coupled gate driving, which would imply using P/N-fets instead of two N-fets. That's actually how I myself have done it before - but I would be very happy to come up with another solution with only N-fets and no AC-coupling on the mosfet gates.
Perhaps using an IR211x-like driver circuit, but with AC-coupled level shifting between the comparator output and the driver circuit?
Or a discrete driver solution similar to the one in the UcD-patent (again with some level shifting needed)?
Or am I completely lost? You tell me!
.Attachments
Oh BTW, for subwoofer power, where class D shines because it permits smooth responding sealed-cabinet speakers to be efficiently fed ample power, the extra propagation delay from the hysteresis in that type of circuit to which I gave the link may be insignificant, so long as the oscillation frequency during clipping does not drop too much.
Well, that is my 2 cents worth. Sometimes the situation carries me away. I have not intended to take the thread from the pursuit of a class D reference design. My topology is not a candidate since it is not suited for full-range sound, but it is easy to simulate!.
Well, that is my 2 cents worth. Sometimes the situation carries me away. I have not intended to take the thread from the pursuit of a class D reference design. My topology is not a candidate since it is not suited for full-range sound, but it is easy to simulate!.
Bricolo said:Chris:
Yes, I tested with more than 100mA
With a 4V RMS input, I see a 18V RMS output on the 6R load
The sine is thick, 1V pp oscillations on it
Yes, the output is inverted.
Before the inductor, looks like a working switching amp
The comparator seems to work, the output is a variable duty cycle squarewave from -25 to -34V
But past the drivers the signals aren't oK
The upper fet's gate swings from +45 to -35
the mower fet's gate swings from -25 to +35, and seems to "saturate" when the output is at it's maximum or minimum
Can you show your schematic with a higher resolution, to see the values, please?
Hello,
I think your problem is evident in the gate drive signals. You need gate to source voltage to be 0 to +12, always with respect to the source!
The great news here is the upper mosfet has a correct drive signal assuming +-35 volt rails? That's the harder one to get right as it has to ride along with the output voltage seen at it's source. Could use even 15 or 18 volt drive signal for faster switching but worry about that later.
Now you have to work on getting the bottom signal to swing between -35 to -35+12.
Good work,
Chris
johanps said:[snip]
Perhaps using an IR211x-like driver circuit, but with AC-coupled level shifting between the comparator output and the driver circuit?
Or a discrete driver solution similar to the one in the UcD-patent (again with some level shifting needed)?
Or am I completely lost? You tell me!
No, I have simulated exactly the circuit you have proposed with the LT1016, using AC coupled mosfet drivers as well as low speed optocouplers to prevent latch-up. I bet the low speed optos could even be replaced with 6N137 ones to make it better.
I wonder if high power can be had without mosfet drivers and their high peak current supplying ability and high input impedance. I seem to be in subwoofer drive mode again.
johanps said:Attached is a small (partial) schematic, intended as a more concrete proposal to stir up some more discussion. (It's embarrassingly incomplete, actually
But it does have a first order loop filter (noise shaper), a comparator, output mosfets+filter, and the feedback.
There's a template for a comparator, which should read LT1016 in the picture! That's a very fast comparator; perhaps too fast for our immediate needs, but it has nice complementary outputs. It does require +/-5V (or just +5V/0V), so it's a bit of a hazzle in that way too. If anyone has a another suggestion, feel free to share it...
Whether the output from the op-amp goes to + or - of the comparator depends on whether the following output drive circuit is inverting or not.
Assuming it's OK to use dual positive/negative supplies (Vdd, Vss) with GND in between, the issue is how to drive the mosfet gates, with suitable amplification and level shifting of the comparator output(s).
Chris (classd4sure) suggested AC-coupled gate driving, which would imply using P/N-fets instead of two N-fets. That's actually how I myself have done it before - but I would be very happy to come up with another solution with only N-fets and no AC-coupling on the mosfet gates.
Perhaps using an IR211x-like driver circuit, but with AC-coupled level shifting between the comparator output and the driver circuit?
Or a discrete driver solution similar to the one in the UcD-patent (again with some level shifting needed)?
Or am I completely lost? You tell me!
Too fast? No such thing
In my defence (I feel the need), when I had suggested AC coupled I was still thinking of a tape and bubble gum 2 cent circuit that could be wired in under 10 minutes.
If we want a bit more quality...throw that idea right out the window, delay is hell on those, and while it can work I dont' think it's actually intended to provide level shifting so much as a bit of a dc offset for the gate signals to help them turn off.
Have you taken a look at the driver circuit in the UCD patent? Check out the circuit I posted earlier. I haven't seen a simpler , or smarter design, and it can be simulated easily, few parts. If anyone can match that without running to a hip4081 or something like it..then I'd say it's a candidate.
+- rails are easy to do and since I think we're all agreed on a simple op amp comparator it'll make life easy.
In the UCD driver the pnp turn off bjt provides the isolation to the drive signal while isolating Rgs from the turn off current. Hard to beat. The other just operates as a simple switch with baker clamp to avoid saturation.
I'll spill the beans on my other drive circuit later on when I at least have it simulating.
That's an interesting implementation of a second order loop.
Wonder how that would affect the phase shift?
Hey how about logic level mosfets driven by a few PVI's?
Ahhhhh how perfect that could be....too bad a fast one doesn't exist.
Regards,
Chris
PS:
I think optocouplers still require floating supplies to work properly in this kind of application? (that's why I like the idea of a faster PVI) That's getting more complicated..and don't forget, they are known for degrading rather quickly, don't want to have to replace them every year!
How did that simulate with the second order loop??
Ok.....I've decided to let it go...here it is...laugh if you must.
My idea for an improved gate driver is that of a pulse transformer coupled gate drive.
From what I've been seeing there's alot of ways this can be implemented. Still trying to decide on the best method, probably with a transistor to speed turn off ...
At any rate I'll probably try simulating a few variations and decide which works best that way.
The problem I've encountered with simulating is the ideal coupling of the inductors/transformers not allowing it to saturate.
Which I've seen can be worked around at least a few ways. Figuring that out will take me some time.
You gain galvanic isolation from the output stage, much like with opto couplers, only they are their own floating supply, which simplifies things alot.
You gain an X type intersection of the On/Off gate drive signals at zero volts, which gives a bit more noise immunity.
Probably higher efficiency, depending.
I don't i'll be aiming for using the trace inductance to be resonant with the input capacitance.....but it's an option too.
With a few variations of it 1 to 99% duty ratios at the required speeds should be easy! This would be perfect as 0 to 100 isn't good anyway.
You gain the ability to easily piggy back more secondaries for driving probably some crazy number of extra half bridges, also making bridging extremely simple.
One thing I haven't put much thought into yet, is how the feedback signal would best be taken, I'd be willing to not use a transformer to pick up the feedback signal from the coil, and just keep it DC connected throwing away the isolation, but still so many advantages to it...
Thoughts?
Regards,
Chris
My idea for an improved gate driver is that of a pulse transformer coupled gate drive.
From what I've been seeing there's alot of ways this can be implemented. Still trying to decide on the best method, probably with a transistor to speed turn off ...
At any rate I'll probably try simulating a few variations and decide which works best that way.
The problem I've encountered with simulating is the ideal coupling of the inductors/transformers not allowing it to saturate.
Which I've seen can be worked around at least a few ways. Figuring that out will take me some time.
You gain galvanic isolation from the output stage, much like with opto couplers, only they are their own floating supply, which simplifies things alot.
You gain an X type intersection of the On/Off gate drive signals at zero volts, which gives a bit more noise immunity.
Probably higher efficiency, depending.
I don't i'll be aiming for using the trace inductance to be resonant with the input capacitance.....but it's an option too.
With a few variations of it 1 to 99% duty ratios at the required speeds should be easy! This would be perfect as 0 to 100 isn't good anyway.
You gain the ability to easily piggy back more secondaries for driving probably some crazy number of extra half bridges, also making bridging extremely simple.
One thing I haven't put much thought into yet, is how the feedback signal would best be taken, I'd be willing to not use a transformer to pick up the feedback signal from the coil, and just keep it DC connected throwing away the isolation, but still so many advantages to it...
Thoughts?
Regards,
Chris
classd4sure said:
I thought the PVI devices I researched were slower than even phototransistor-based optos. But it could just be a mental lapse on my part.
I should qualify that I omitted the integrator portion and simulated with the circuit after the comparator onward. It was a few months ago and I did it in LTspice with which I am not completely proficient. It seemed to show promise, though.
subwo1 said:
Yeah the the PVI's are totally useless
At least the ones I've seen. Some advancements in that area would sure be nice for class d anyway, a one part gate driver.How bad was the noise you experienced with the pulse transformer and what was the source, RFI?? Was it enough to be unusable? Could it have been worked around somehow..snubbed...isolated?
Another disadvantage I can think of for it is the requirement of a beefy buffer to drive the primary.
There must be some difficulty making it work right or gate driver IC's wouldnt' exist right, but I have seen a 13Mhz @ 5kw from ixys using a resonant version of it, also it seems to be a big thing with tesla coil drivers where they need the isolation, not sure if it's worth giving up on just yet.
They'd also throw off alot more noise..
Really I'd like to keep it as simple as possible, have the same level of performance, and just add some negative gate drive somehow.
Suppose it would be easiest to simply design the given driver properly, but if I didn't at least add a personal touch, I'd feel like I ripped it off
I go off on the perfect circuit tangent at times but it's a good way to learn new things.
Bricolo said:
Sorry, I'd like to help ya with that but I can't. All I can do is take screenshots with it, if I zoom in enough to see the part values better I'll only be able to get 1/10 the circuit in the screenshot, then I'd have to flood the forum with a bunch of partial circuit badly implemented screenshots ....
Not my design but I'm fairly certain there's an integrating component in the feedback loop itself, the cap?
See how simple and compact it is? The more you learn about it the more you'll be impressed I promise.
I'm still uncertain as to how the gate drive signals are biased in your design but I'm sure Charles won't mind filling us in.
In spice you can simply the current source above the comparator with an ideal one, as someone already stated I think. One problem I encountered .....is that simply didn't work good? I wasn't able to minimise the dc offset with that.
Now I'm simply using 1 resistor in it's place, and it's working so good I'm wondering if there's a point to using anything more, if it's all powered by the same rails, compliance isn't a factor....might improve supply rejection?
The lower you can take the current to power the comparator the better, I still haven't been able to get it very sensitive to input though, but the DC offset is way down.
The rest of your circuit is fairly ideal so values shouldn't be much of a problem.
I might give that circuit a shot later there's a few things I'm curious about with it, though I haven't yet had much luck with those ideal switches. I'll let ya know.
Chris
classd4sure said:
I did not think of using a classic RC snubber, but I did try a basic damping resistor. I played with wider band transformers than pulse types, though I did wind them myself on mini toroid cores. They are somewhat tedious to deal with. That is why faster optos would be excellent because they bypass such effects as inter-winding capacitance. Now, I must say that I was playing around with mosfet drive for an SMPS which didn't need even as much as a 50% duty cycle.
TI has a PWM chip which supposedly is able to drive a totem pole bridge with 3 amps of peak current through a coupling transformer. It modulates the transformer by variably delaying the drive to one side of the bridge, a transformer in the case of the data sheet was the load. The IXYS approach sounds similar. But the TI chip has a propagation delay figure of no less than 50ns.
subwo1 said:
Then I guess neither IXYS' or TI's solutions would be good ....sounds alot like BCA junk.
I'll dig up the diagram of one or two of the pulse transformer implementations I had in mind and post em here just for kicks.
I'm starting to lean away from the idea though.
Those darn opto's....are such a tease aren't they?
I thought of even using a PVI as an overly simple gate drive power source, but they need an off period ..
You can get opto's fast enough, and they're a brilliant idea, but the derating they suffer is disgusting and there's just no way around it.
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