Complementary diff input with JFET and BJT cascode

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bocka said:
Hi Bensen,

voltage loss of a folded cascode can be reduced to 2-3 volts, very similar to what in a cascoded VAS can be done. In a folded cascode forget about Q3 connect the base of Q4 directly to Q2. R1 can be omitted. Voltage across R2 should be choosen of about 2 volts. To perform this, use two red LEDs to V+ on the base of Q4 for example. Bias through Q2 should be a little bit higher than the sink current Iq of the LTP. So

R2,max = 2V / (2 * Iq)

To prevent oscillation, use a cap of about 100pf from the collector of Q4 to GND. This is a nearly bullet proof solution.



Because the transistor models are too bad (especially for high frequencies) and a sim cannot take parasitaric effects of the real setup into account (i.e. a schematic and this is what a simulation uses, is only a very idealised model of your real circuit)

Hi Bocka,

I've managed to build the circuit in spice. The first simulations are looking promising. The amp looks more stable.
But, the total gain isn't big. I manage to get about 8000x. And compared with the cascode VAS, I could easily have about 20000x.
What do you think? Can you suggest something to increase the gain?

Greetz
Ben
 

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forr said:
My previous post and the thread have made me to think of this symetrical preamp due to Linsley-Hood which may interest some amp specialists.

~~~~ Forr

§§§


Hi Forr,

What do you gain by using that topo? I can see that the gain increased (x2 I guess), but also that you have a bit more voltage loss --> efficiency drops. Gian is mostly no issue with cascoded VAS'es.

Greetz
Ben
 
But, the total gain isn't big. I manage to get about 8000x.

Hi Ben,

yup, I wouldn't expect more, because you only have a SINGLE amplification stage. But why you want to have a higher DC high open loop gain? If you have an open loop bandwidth of lets say 5 MHz and a single pole compensation, the gain at 5 kHz is only 1000. This is independant of the number of stages and of the OLG. An audio amp is no precision Op-Amp and don't need a high open loop gain.

For stability reasons add a cap (about 100pF) from the collector of Q1 and Q2 to GND. Otherwise you will have oscillations.
 
bocka said:
Ummpf,

should have taken a closer view to your schematic. Omit also the second diff amp and connect the folded cascode directly to the first LTP like post #59. Remove R20 and R21. They're only lowering the OLG and do nothing good in my opinion.

Ok,

Remember, when I would omit the second diff amp, I would have a gain of only +-800. I don't think this is sufficient to keep THD low. I red a few times that amps with JFET in anD MOSFET out designs, sounded harsch. But when I see the schematics of these amps, they all have pretty low gain. I think this is the reason for the harsch sound, I don't know for sure.

But 800 is to low. Does anybody have an idea of what the gain minimal should be in such a design? I've designed the amp to have a gain of +-20000. This is the average of a bunch of schematics I've seen.

The resistors R20 and R21 are indeed decreasing OLG, but they also help to stabilize the amp. This is one of the trics Elektor uses always in each of them designs. I beleive them.

Greetz
Ben
 
Hello all,

I hope to end the design off this amp in a couple of weeks. Has anybody an opinion of using a emitter follower after the VAS? Is this really a must to have, or can one say that is has its pro's en con's in my design?
I'm aksing this question because, when I don't use this EF I have no troubles to get the amp stable. Even without miller caps and local feedback.

See the attachment in this post to have an idea what I mean.
http://www.diyaudio.com/forums/attachment.php?s=&postid=757679&stamp=1130955261

Greetz
Ben
 
Hello all,

I finished the schematic of the amp. Maybe still a few resistor's will change.
Can you guys take al look at the circuit, if you see something strange of something that could be better, please tell me.

The only thing that is not at this schematic is the DC-servo.

The people of Donberg told me that the 2SJ109BL and the 2SK389BL devices are on the way to here. they had some troubles finiding these. I know that these weren't the easiest devices to find.

Sim's:
Vin: 1.28V 10kHz --> THD 0.007%
The THD figures are between the 0.03 and 0.005% with different voltages and frequency's.

Greetz
Ben
 

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Hi Bensen,
the 2nd 3rd and 4th harmonics do not even rise out of the minimum resolution of the measuring system at -63db to -64db.
At 0.07% I would expect to see one or two harmonics of 10kHz.

Is there any way to improve resolution with your system, maybe averaging? So that you can at least identify that you are measuring something.
 
AndrewT said:
Hi Bensen,
the 2nd 3rd and 4th harmonics do not even rise out of the minimum resolution of the measuring system at -63db to -64db.
At 0.07% I would expect to see one or two harmonics of 10kHz.

Is there any way to improve resolution with your system, maybe averaging? So that you can at least identify that you are measuring something.


Andrew,

When I set the simulation time at 10 periods. The THD rises till 0.5%. Now I can see clearly the 2nd untill the 7th harmonics.
2nd: -26dB
3th: -23.3dB
4th: -28.7dB
5th: -21.2dB
6th: -25dB
7th: -27.3dB

But I once red some rules about simulating. One said that the best practical results are measured with simulation times equal to 5periods.
 
AndrewT said:
Hi Bensen,
1n748 giving almost 3V, what is it?
34mA through 33r is only 1V1 bias across the output stage. This does not add up? I would expect two to three times this amount of driver bias, which is why I asked. 33r seems VERY low.



1N748 is just a zener diode of 3.9Volts. The regular zeners aren't in the library of LTSPICE.

Yes, correct, the voltage over the 33R resistor is 1.15V. This gives me a quisent current of about 115mA/MOSFET. Do you think 34mA throught the drivers isn't enouph?
When I increase this resistor, the idle current throught the drivers will decrease.

Ben
 
Bensen said:



Andrew,

When I set the simulation time at 10 periods. The THD rises till 0.5%. Now I can see clearly the 2nd untill the 7th harmonics.
2nd: -26dB
3th: -23.3dB
4th: -28.7dB
5th: -21.2dB
6th: -25dB
7th: -27.3dB

But I once red some rules about simulating. One said that the best practical results are measured with simulation times equal to 5periods.

Hi Andrew

Switch off "compression".

Be shure that You set Your simulationtime so that You see 3 or 5 or more c o m p l e t e cycles.
E.G first cycle starts at 0V and also the last should stop there exacly.

Switch off "compression" ("tools-control-panel").

Set the simulation-time-step m u c h smaller.

Do first a test with Your inputsignal!

You can reach easy -180dB!

Regards
Heinz!
 
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