alfsch said:
I made something like this. It's very similiar, only with little different feedback. Supply is +-35V. Comparator is LM311. Mosfets ( IRF530/IRF9530n ) remains cool, but there is a problem. Zeners heats up badly ( maybe +-35V is too much for this circuit ? ). Any comments ?
Can you show us pics from that German site ? I'm member but not active ( have no access to the projects ).
Hi, Alfsch,
What do you think about output stage in ZXCD1000 datasheet? Similiar to your output stage, the driver is only 9V, yours is 20V (+/-10V).
I think that cross conduction (or too much dead time) is very dependant to this driver's voltage (9V to 20V giving different dead time/cross conduction).
Do you have idea how to make adjustable dead time for your schematic?
What do you think about output stage in ZXCD1000 datasheet? Similiar to your output stage, the driver is only 9V, yours is 20V (+/-10V).
I think that cross conduction (or too much dead time) is very dependant to this driver's voltage (9V to 20V giving different dead time/cross conduction).
Do you have idea how to make adjustable dead time for your schematic?
R8,R9 - I saw that in some older designs ( PMOS is slower than NMOS... ). But in simulations there is no difference ( maybe because i'm using IRF530/IRF9530N ). They have similar Qg,...( new Pmosfets are much better than old ones ). I will try with 47ohm both.
R12, R13 - They prevent huge gate currents. Without them, mosfet discharges trough zeners ( I'm not sure, but saw that in simulations ).
R12, R13 - They prevent huge gate currents. Without them, mosfet discharges trough zeners ( I'm not sure, but saw that in simulations ).
R8,R9 set on delay = dead time
size depends on real gate-kap. , simu wont help here
with my (old) irf 530/9530 those values gave good result, if you have new fets, just test...most time the p fet has bigger gate.kap. , so it needs smaller r.
r10/11 are just keeping the gates at zero Vgs , if no signal at gate , i.e. on power on
value can be much bigger, about 50 k, maybe 100k, depends on: how fast is voltage rise at power-on.
size depends on real gate-kap. , simu wont help here
with my (old) irf 530/9530 those values gave good result, if you have new fets, just test...most time the p fet has bigger gate.kap. , so it needs smaller r.
prevents rf-oscillations and limits turn-off speed
r10/11 are just keeping the gates at zero Vgs , if no signal at gate , i.e. on power on
value can be much bigger, about 50 k, maybe 100k, depends on: how fast is voltage rise at power-on.
the comp.supply adjusts itself by the output-power going into the zeners at the gates. so driving this supply with a low impedance source is no good idea
right, but i drive the gates +/- , not only +/0 , which makes a very simple shoot-throu prevention possible: when one fet goes off, voltage at the other can be set so low, its just turning on or still off , depends on the r
alfsch said:
Hi,
I guess its the latest.. I re-downloaded it because I seem to have misplaced the "old 2 year ago" version... the new one I have just downloaded recently(a week perhaps)... seems your sim file posted is old??
EDIT:
AND I have also built the said circuit... it kinda sounds ok BUT I can still hear some distortion(on the low freq part of input....) I think Its in the deadtime settings...
Thats why I really SHOULD see "scope waves" in LTspice...
after seeing this post resurface i thought i'd have a look at the d amp schematic.
I'd say it definately is self oscillating because it has a positive feedback loop.
The filter in the feedback loop probably sets the oscillating frequency.
There is a simulation file in the earlier bits of the thread, check it out.
...and d/l lt spice switcher cad iii if you havent already.
I'd say it definately is self oscillating because it has a positive feedback loop.
The filter in the feedback loop probably sets the oscillating frequency.
There is a simulation file in the earlier bits of the thread, check it out.
...and d/l lt spice switcher cad iii if you havent already.
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