Cheap 24/96 DAC, Revision B.

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Send me a private message (it appears you have turned off email in your preferences).

BTW, to make sure there's no power supply problem, you should be able to run the thing on two 9V batteries in series (connect + of one to - of the other, and use that as a virtual ground; the other ends to the +/- power inputs, making sure not to accidentally switch the polarity as that will fry the thing). Due to the current draw the batteries will last very little time, but should be enough to test it.
 
Would a bench supply work? I have two. The main one I use has two positive variable outputs (both with seperate grounds) and a positive 5V output. I have other, smaller bench supply with a positive 5V output, a variable positive and negative output that share the same ground. Can I use my main one to drive all positive 10V inputs using one variable output and use the other variable output but reverse the polarity for the negative 10V input of the DAC?

Thanks.
 
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Thanks, greyhorse.
I'm not complaining, just trying to understand what's going on :)
I'd like to ask how the resistance changes things, as the chip still has to deliver the same charge to the gate in both cases, so the same current over a given time.
IRF application notes 437 and 444 talk about calculating drive requirements and maximum frequency from gate charge (figure 6 in the IRF610 datasheet is the gate charge vs Vgs), but for switching applications. So how do you calculate in this situation?

One more question. Can I put a cermet potentiometer before the buffer for volume control, or will that, combined with the IRF610 capacitance, make a filter low pass enough to affect the audio band?
 
Ok, the CS8420 came, but as I suspected, it still would not work. Somone gave me the idea of using a logic probe. So, I did, I've notice the resistor network by the CS43122 never pulled the pins it was connected to high, so I soldered them and now they are all high. I looked at the master clock, and the "pulse" LED on my logic probe flickers. I looked at the serial and left right clock and they pulse as well. The data line seems to remain low, but on occasion pulses. I hear intermittant pops, and digital static every now and then. I suppose I'm getting closer, but this is only when the logic probe is connected. I'm suspecting the resistor arrays connected to the CS8420 are to blame. Am I correct when I assume that the resistors connected in series with the pins and ground should be low? Same if the resistors are connected to Vcc? Pin 25 and 28 on the CS8420 should be low, but I measure them as high. I'm sure resistor arrays can withstand a good amount of heat. Or are these pins suppose to be high?

Thanks.
 
Prune,
The problem with capacitive loads on the output of amplifiers is described in the following article, along with how a resistor works to help stabilize the amplifier.
http://www.analog.com/Analog_Root/s...ols/interactiveTools/stability/stability.html
You’ll notice that the value of this resistor has to be adjusted to achieve optimum performance. In the case of JWB’s DAC, the series resistors are actually part of a filtering network (along with C33/34), and are the same values used in the 43122 evaluation board. The additional gate capacitances of the FETs seem to be small enough not to cause any problems.

As for adding a potentiometer between this filter network and the gate of the IRF610s, I’m not sure. It’s a very similar configuration to what is used in the Szekeres headphone amplifier featured in the Headwize projects pages. I like the idea of getting rid of a possible preamp, and directly driving a power amp with the DAC. I’d say go for it, and see what happens.
 
What greyhorse said is correct. The output of the DAC is driving the gate through an RC network. There should be no stability problems. If you felt like it, you could replace the entire line driver with a good opamp, but that would remove some of the Yourself features of this DIY project.

There are three working instances of this design to my knowledge. If you are looking for design defects you are looking in the wrong place.
 
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jwb, I'm not looking for design defects! My instance of your DAC design has been working fine for months, so you can add it to your count! Rather, what I'm after is adding a volume control before the buffer without making this too hard a load for the CS43122. In another thread I've discussed whether a potentiometer combined with the input capacitance of the HEXFETs could be a problem. A Borbely JFET follower seems one possibility; additionally, it has no DC offset so I can use smaller quality caps at the gates instead of large expensive ones at the output. Plus, it only needs a dual gang potentiometer for both balanced channels. With such a setup I should be able to drive an Aleph-X directly, without a preamp (putting a volume control in front of the Aleph-X is a problem since it already has a 10K shunt-to-ground resistor at the input, and I'd have to use a very low value potentiometer). In the picture below, input comes from the analog filter after the DAC chip.
 

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Prune said:
Rather, what I'm after is adding a volume control before the buffer without making this too hard a load for the CS43122.


Prune,

If you are tinkering with this design and want to add a volume control you should try adding a mono pot to attempt to scale down Vref pin of the DAC.

I've been curious to try this for a long time and these Crystal DACs are ideal canditates for this, AFAIK you +5V analog supply is only used for Vref. If the DAC works well with lower values you get the benefits of a passive analog volume control with no output impendance effects and no channel tracking issues (ie you don't need a stereo pot).

There is no mention in the datasheets about Vref being anything other than 5V typical. I am really curious about the performance below that since this is a delta sigma dac so it should work just as well with any reference voltage within limits.
 
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The analog supply also goes to VA, so I can't mess with the regulator output. I don't know what current VREF draws, and whether a pot as a voltage divider would work for VREF.

I'm going to start a new thread to get comments on the performance issue. In the datasheets, they used 5.5V for their performance results.
 
Hi fellas, I'm a long time lurker, first time poster here at diyAudio.com. This seems like a great little project. I want to build a couple of these to use for experiments with output stages (tubes, transformers, opamps, video buffers etc) and power supplies and clocks or whatever strikes my fancy. I want to embark on a project like this really for my own digital audio education.

I'm wondering however, whether anyone can comment on the sound of this design, particularily if you can compare it to a high-end CD source such as the Perpetual Technologies DAC or Gamut CD player (which also use AD43xx DACs). Or any other modern source that I may heard at a dealer or audio show. Or, has anyone compared this to other popular DACs like Scott Nixon's or Ack's DACs for example?

Actually, I'd really appreciate *any* opinions because I have no idea what to expect sonically from this design. All I know is that I like the parts and design approach from what I understand so far.

Thanks,
Anthony
 
I like the sound of this DAC, it has a good, clean sound that reminds you how few components are involved. With very strong highs it doesn't sound harsh like most consumer-level DACs, which I think is a benefit of the ASRC and a good local clock.

Compared to my only other DAC, a quad-PCM1704 design with ASRC, it doesn't sound quite as good. The TI DAC has much less background noise. I think that's because it is on a huge four-layer PCB, and has a custom clock. But the "cheap" DAC sounds better than mid-range implementations like the NAD C541i.
 
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Hi jwb,
I just noticed an updated CS8420 datasheet on Cirrus' website. It says the following for rectifying the invalid mode bug ("notches occurring in the frequency response, and spurious tones being generated in response to some input frequencies") when in hardware mode:
In Hardware mode, monitor the RERR pin for receiver lock status. When the part achieves lock, set the RST pin low for at least 200 µs and then set it high again. This action clears the invalid state if it has occurred. When polling the RERR pin again, the user must account for the fact that the RERR pin will be high during reset and remain high until the PLL has reacquired lock.
Is it difficult to automate this? Also, can I manually do this by simply powering off and then on the DAC?

I also noticed this errata from October, saying:
due to process differences between the original foundry (revision D) and the new foundry (revision D1) it is necessary to change the external PLL filter components for reliable operation.
The values given are very different. This errata is dated October, whereas I got my CS8420 in May, so I belive I have revision D, but those that are building this DAC should check what revision of the CS8420 they have as described in the errata.

Also, you mention background noise. This noise is pretty low (I have to turn my headphone amp most of the way up to hear it with my HD580), but I find it doesn't change even when I tried feeding the PCB from 9V batteries and I bypass the output buffer. What causes that noise?
 
Prune,

I think the noise has a few different causes. Firstly the proximity of the DAC to the rest of the electronics. Some noise is going to be inductively coupled. Secondly my main supply is poorly regulated, which can add some noise in the output buffer. Thirdly I think I am picking up some noise from free air (poor chassis shielding).

The errata is a pain in the neck and there is no workaround, in hardware mode, except to throw the power swtich off then on. The only way to workaround it is with software and a microcontroller. If you never plug/unplug the input you might not have problems. I usually turn on the CD player first, then the DAC. In my next DAC I'm trying to avoid Cirrus Logic because the CS8416 has exactly the same problem!

I was thinking some about your ideas to integrate the attenuator into the output of the DAC. One way would be to discard my line buffer and replace it with a scaled-down Balanced Zen Line Stage, from Nelson Pass' article in Audio Electronics, 5/1997. If you add a pot between the drains of Q1 and Q2, it acts as an attenuator. You might give that a try, the BZLS is fairly easy to build.

PS: I was hanging around on Headwize and I noticed you were driving headphones directly from this line buffer! You are insane! How did that sound? I can't imagine it was able to provide much more than 10mW per channel.

Cheers,
jwb
 
Speaking from design experience with the CS8420, it's not a good chip. The reset trick talked about in the 'invalid state' part of the datasheet works 90% of the time, but not always.

It's a shame, because when it works, it's a damn fine chip.

Implementing the reset trick could be done using a PIC12C508a or similar microcontroller... I'd much sooner use a CS8416 or DIR170x receiver, combined with a separate AD189x or SRC419x SRC.
 
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