The SRC4192/3 has vastly better specs than either of the two Analog or Cirrus parts, also. It's the one I'm using but I'm wary of the DIR1703. It's datasheet is filled to the brim with errors. I think I'll stick with CS8416 but I'm afraid it has already accumulated significant errata.
Perhaps the CS8415 is still the best choice?
Perhaps the CS8415 is still the best choice?
Hey jwb,
That's a real bummer, considering I had just got a few cs8416's. Have you looked at any of the AKM chips, like the AK4117? I know its a pain to get a hold of considering you have to purchase $50 worth of semi's from their american distrubitor All American direct, but maybe its worth it. Akm has a pretty good reputation, and I think I'm going to get a hold of their chips sometime down the line. Their 192khz dac is used in some high end pro equipment with positive results.
Later...
That's a real bummer, considering I had just got a few cs8416's. Have you looked at any of the AKM chips, like the AK4117? I know its a pain to get a hold of considering you have to purchase $50 worth of semi's from their american distrubitor All American direct, but maybe its worth it. Akm has a pretty good reputation, and I think I'm going to get a hold of their chips sometime down the line. Their 192khz dac is used in some high end pro equipment with positive results.
Later...
I've yet to find any practical problems with the CS8416 here. There is an issue with RMCK not properly switching over if you're using the OMCK input, but if you're using it with a SRC then you're not using RMCK/OMCK anyway and you shouldn't run into any trouble. Driving a DAC directly? don't use OMCK.
As for the DIR1703 receiver, could anyone here actually *comprehend* the datasheet? I can't tell if the chip does anything at all... also, anyone know what people are using for RS422 receivers to accompany the DIR1703?
As for the DIR1703 receiver, could anyone here actually *comprehend* the datasheet? I can't tell if the chip does anything at all... also, anyone know what people are using for RS422 receivers to accompany the DIR1703?
Individuals from Mars and deep Space
Hi gmarsh,
The datasheets from Crystal/Cirrus are written by an individual coming from Mars but my best guess is that the Texas Instruments DIR1703 datsheet is written by an Alien from Deep Space. I have re-read it many times and I can only understand the schematics though the 3.3V issue is not very clear either.....
gmarsh said:
Hi gmarsh,
The datasheets from Crystal/Cirrus are written by an individual coming from Mars but my best guess is that the Texas Instruments DIR1703 datsheet is written by an Alien from Deep Space. I have re-read it many times and I can only understand the schematics though the 3.3V issue is not very clear either.....
In my case, I know it's not power supply noise (same noise level when I use batteries to power the whole thing), and not shielding (I have outer chassis, and separate inner chasses for power supply and DAC, all star grounded). It basically sounds like white noise, but it's inaudible with 300 ohm headhones unless I turn my headphone amp all the way up (I think it's below the level of any actual tone, so it may not be all that far from spec).jwb said:
In the latest datasheet revision, they discuss hardware mode, resetting it as soon as the PLL locks to a stream (as I quoted in post 180). I think this can be implemented with a some flip flops and few gates. The trick is not to reset again the first time RERR goes low after a reset. I came up with a four state automaton.
I think I'll just use the JFET follower from post 174, as it's very simple and only needs a dual pot for stereo balanced control, and the capacitors are not at output, so I can use much smaller and fancier ones.
Only thing is that I can't figure out how to use the log-faking shunt resistor trick that's can be done to volume controls when a linear pot is wired as a voltage divider. In the circuit I posted before the pot is wired as a variable resistor. Is there any way to fake a log control with a linear pot in this configuration?NO! I'm using a tube headphone amp. I did try driving directly 300 ohm HD 580, but there wasn't much distortion, just not very loud and lacking bass.
Do you mean what I quoted in post 180? Can you tell me specifically in what situation it doesn't work? BTW I've never noticed the invalid mode myself; I guess I've been lucky (or have really poor earsgmarsh said:
-- does the invalid mode really stand out, or is it a bit more subtle?)
The 'invalid mode' is far from subtle... it sounds like the shift register that receives data from the AES stream isn't shifting the right number of locations. Sometimes the audio is quiet but sounds OK, sometimes it's loud and "clipped", sometimes it's extremely distorted, and sometimes you just get pure garbage. The AUDIO and RERR pins would indicate that everything was fine.Prune said:Do you mean what I quoted in post 180? Can you tell me specifically in what situation it doesn't work? BTW I've never noticed the invalid mode myself; I guess I've been lucky (or have really poor ears
Here, we ran the part in hardware mode, with a 96KHz output sample rate, the "32-96KHz" PLL loop filter components, and unplugging/replugging an AES cable (carrying a 44.1KHz stream) multiple times would upset the 8420.
If I didn't reset the 8420 after the PLL locked, about 1 out of 2 times I'd hit an invalid state. If I followed the reset procedure, about 1 out of a dozen times it'd still mess up. When you're trying to build high reliability stuff like radio broadcasting equipment, you can't have this stuff happening...
Resetting the 8420 seemed counterproductive to me - you had to do it after the PLL locked, but resetting the 8420 causes the PLL to unlock and then lock again.
Whoa! I never heard anything like that in all the time I've been using this DAC. I use relays to switch between streams, so there are plenty of interruptions in the incoming streams. I wonder if there's a difference between the various revisions of the chip. The only thing that I have noticed is that sometimes when input stops, the last sample keeps playing nonstop instead of silence, but I don't know if that's a problem with the DAC or the ASRC.
The point is this: invalid mode can occur when an input stream is interrupted or begins again. What they are saying is that to deal with this in hardware mode, any time a new stream begins, you want to reset the chip so it comes out of reset with a stream already playing. When the PLL locks again the chip is now supposed to be in valid mode.
Since I don't know any microcode programming nor have equipment, I think this can be done with flip flops and a few gates that implement an automaton somethig like this:
In jwb's DAC, RST is tied to the output of a voltage monitor that makes sure there's power and then takes off reset. RERR is pulled high by a 47K resistor as a startup option. I'm thinking something like this:
Four states: OFF (keep RST 0), ON (RST 1), CLEAR (RST 0), and VALID (RST 1). OFF is starting state when power is applied.
any state->OFF when VM=0
OFF->ON when VM=1
ON->ON while RERR=1
ON->CLEAR when RERR=0 (on falling edge; start Timing)
CLEAR->CLEAR while not Timeout
CLEAR->VALID on Timeout
VALID->ON on RERR=1 (on rising edge)
VALID->VALID while RERR=0
It must be the SRC doing that - it probably loops through a FIFO or something when it loses its input. In our case, we're feeding the output of a SRC into a DSP and we've noticed the same thing.Prune said:
I should capture some .wav files of the chip's behavior at work tomorrow (if I get some free time) of the various "states" that the chip goes into.
I'm using the "D" version of the chip, I think...
Wow, now that's persistence.
I've made a modification to mine, and doing another one as soon as I get the rotary switch. I highly recommend both. The first one is an automatic reset circuit that deals with the occasional invalid mode bug that the CS8420 has. It is referred to in the latest datasheet (version 5 as of the time of this post) as well as how to avoid it in hardware mode (luckily no microcontroller is needed). The other one adds a volume control (and changes the buffer), so a preamp is not needed.
The attachment is a zip archive with three files. The simple reset circuit is in rst.png. Power supply to the logic is not shown; just use the 5 volts from the DAC's digital regulator and put a ferrite bead and some small capacitance. LTSpice didn't have a J-K flip flop, so I used a D in the schematic. In the actual build I used a J-K, I think a 4027 (with a J-K, to wire for toggle operation, connect both J and K to high). The NE555 is easy to find. C1/2/3 should be film or ceramics that are stable with temperature changes so as not to mess up the timing. The 47K resistor remains from the original circuit as a startup option. For the inverters I just used a quad 2-input NAND gates IC (both inputs of a gate tied together). What's not shown is that the voltage monitor output should be ANDed with the output of this circuit (with the NAND gates just NAND using one, and invert with the other one; you need exactly four gates = 1 IC for this circuit).
The way this works is that every lock (RERR goes low, and yes, despite the pull-up resistor) the J-K is toggled; every other toggle gives a falling edge to Q' and C3/R3 convert it to a low pulse that triggers the timer (set to 1.1 ms which is plenty long given the datasheet says at least 200 us). The timer is active high, so that's inverted and ANDed with the voltage monitor to control RST'. If you draw a timing diagram you'll see that after every stream interrupt, when it locks on a stream the first time (which is when an invalid mode can exist) it is reset; then it relocks on the stream and is not reset again until next time.
To make sure this is built correctly, try bypassing C2 with a large enough capacitor to visually see the delay (monitor output with a LED that of course has current limiting resistor or it doesn't work right; if using a switch to provide input for testing, it doesn't work good due to contact bounce doing many flips when the switch is switched; better use some other pulse source). IMPORTANT: I tested 4027 from both TI and Motorolla, and both flip flops booted at power on with Q/Q' at 0/1. So I didn't bother trying to figure out how to initialize SET/RST at startup and left both on low. If this assumption is wrong and it starts up backwards, it will mess up the counting and not reset properly on the first stream (should be fine after).
The other modification is shown in buf0.png. The volume control is R4, so you only need a dual attenuator for balanced volume control. If you put this volume control in front of MOSFETs, together with their input capacitance (or the interconnect capacitance if you should put the volume control after the buffer instead) creates a low pass filter. I replaced the MOSFET buffer with the simple JFET buffer, as JFETS have much smaller input capacitance. The DC blocking capacitors are now on the gate side and thus much smaller, meaning you can get fancier caps (I used 0.68 uF Sidereal capacitors from partsconnexion, which are Auricap predecessors that are the same but with solid leads, which I think is better anyway).
I replaced the SMD 300R resistors and 2200 pF capacitors with Caddock MK132 resistors and silver mica (polystyrene is better but I couldn't find it; these also from partsconnexion). The capacitor is smaller at 1000 pF since I like less rolloff in the high end (and simulation shows less phase shift). I also used the MK132 for the 1K and upper 10R in each JFET pair, but this gets expensive quickly, so for the rest I got Roderstein MK3 from percyaudio for 25 cents a piece, and they are still excellent resistors with good tempco.
If the buffer is powered from the same supply as the rest of the DAC, put a ferrite bead and then 100 uF to ground on each rail. The buffer's DC offset is minimized if the +/- supplies are close in magnitude. By trying various 2SK389 (I got the JFETs from bdent) you can try to get a smaller offset; then minimize it completely by adjusting the lower resistors on each pair, you should get below a mV. Note that the JFETs are dual, and if you swap which half is used as the first and second JFET, you change the sign of any leftover DC offset; it's better to have such offset on both balanced lines the same sign so it's mostly common mode. Also, hifizen pointed out that some amplifiers such as Aleph-X should be AC coupled to this kind of buffer so current is not sent back into the buffer in case of DC offset in the Aleph-X; so maybe 10 uF for DC blocking, but I would put it on the amplifier side as it depends on what you are driving.
IMPORTANT: You cannot use a potentiometer or existing attenuator for R4, as the attenuation you'll get is no good. The curve needs to be logarithmic but more so than standard log pots; they won't give you a good result. You need a blank rotary switch (cheapest acceptable I found is Electroswitch C7D0223N from digikey). For the resistors I also used Roderstein MK3 from percyaudio. The values are given in the spreadsheet attenuator.xls. Column R' gives the closest actual resistances you can get to minimize the difference in attenuation between this and the optimal (resistors in column R). These are for a 24 position switch. For a 23 position, skip the last 1.96R resistor. The calculation takes into account that the 300R filter resistors and 500K (I used 511K) gate resistors are also part of the voltage divider volume control along with the 1K and the attenuator. What is NOT taken into account, however, is the output impedance of the CS43122, as that is not given in the datasheet and due to the switched capacitor output of this DAC I'm not sure it's a meaningful measure (that's why they only specify limits on the load). I don't think that will have any significant effect, so the resistances should make a properly behaving attenuator.
The Step column in decibels must be credited to the Goldpoint website, so I figure they know what a proper attenuation curve should look like. The reason that the attenuation column doesn't start at zero (max volume) but instead a bit lower is that even when R4 is open (infinite resistance), the gate resistors are parallel with it and limit the maximum possible volume. The voltages are given peak-to-peak. The input is assumed 7.3 V, because when I tested with a multimeter, I got about 2.5 rms on a 60 Hz sine (with the old buffer), which gives about 7 V peak-to-peak, indicating that what someone said in another thread that they must have meant 1.33*common mode instead of 1.33*VREF is mistaken, or I measured wrong (doesn't affect the resistance calculation anyway). Higher swing voltage than the power supply is possible since the output is capacitor switched.
I've made a modification to mine, and doing another one as soon as I get the rotary switch. I highly recommend both. The first one is an automatic reset circuit that deals with the occasional invalid mode bug that the CS8420 has. It is referred to in the latest datasheet (version 5 as of the time of this post) as well as how to avoid it in hardware mode (luckily no microcontroller is needed). The other one adds a volume control (and changes the buffer), so a preamp is not needed.
The attachment is a zip archive with three files. The simple reset circuit is in rst.png. Power supply to the logic is not shown; just use the 5 volts from the DAC's digital regulator and put a ferrite bead and some small capacitance. LTSpice didn't have a J-K flip flop, so I used a D in the schematic. In the actual build I used a J-K, I think a 4027 (with a J-K, to wire for toggle operation, connect both J and K to high). The NE555 is easy to find. C1/2/3 should be film or ceramics that are stable with temperature changes so as not to mess up the timing. The 47K resistor remains from the original circuit as a startup option. For the inverters I just used a quad 2-input NAND gates IC (both inputs of a gate tied together). What's not shown is that the voltage monitor output should be ANDed with the output of this circuit (with the NAND gates just NAND using one, and invert with the other one; you need exactly four gates = 1 IC for this circuit).
The way this works is that every lock (RERR goes low, and yes, despite the pull-up resistor) the J-K is toggled; every other toggle gives a falling edge to Q' and C3/R3 convert it to a low pulse that triggers the timer (set to 1.1 ms which is plenty long given the datasheet says at least 200 us). The timer is active high, so that's inverted and ANDed with the voltage monitor to control RST'. If you draw a timing diagram you'll see that after every stream interrupt, when it locks on a stream the first time (which is when an invalid mode can exist) it is reset; then it relocks on the stream and is not reset again until next time.
To make sure this is built correctly, try bypassing C2 with a large enough capacitor to visually see the delay (monitor output with a LED that of course has current limiting resistor or it doesn't work right; if using a switch to provide input for testing, it doesn't work good due to contact bounce doing many flips when the switch is switched; better use some other pulse source). IMPORTANT: I tested 4027 from both TI and Motorolla, and both flip flops booted at power on with Q/Q' at 0/1. So I didn't bother trying to figure out how to initialize SET/RST at startup and left both on low. If this assumption is wrong and it starts up backwards, it will mess up the counting and not reset properly on the first stream (should be fine after).
The other modification is shown in buf0.png. The volume control is R4, so you only need a dual attenuator for balanced volume control. If you put this volume control in front of MOSFETs, together with their input capacitance (or the interconnect capacitance if you should put the volume control after the buffer instead) creates a low pass filter. I replaced the MOSFET buffer with the simple JFET buffer, as JFETS have much smaller input capacitance. The DC blocking capacitors are now on the gate side and thus much smaller, meaning you can get fancier caps (I used 0.68 uF Sidereal capacitors from partsconnexion, which are Auricap predecessors that are the same but with solid leads, which I think is better anyway).
I replaced the SMD 300R resistors and 2200 pF capacitors with Caddock MK132 resistors and silver mica (polystyrene is better but I couldn't find it; these also from partsconnexion). The capacitor is smaller at 1000 pF since I like less rolloff in the high end (and simulation shows less phase shift). I also used the MK132 for the 1K and upper 10R in each JFET pair, but this gets expensive quickly, so for the rest I got Roderstein MK3 from percyaudio for 25 cents a piece, and they are still excellent resistors with good tempco.
If the buffer is powered from the same supply as the rest of the DAC, put a ferrite bead and then 100 uF to ground on each rail. The buffer's DC offset is minimized if the +/- supplies are close in magnitude. By trying various 2SK389 (I got the JFETs from bdent) you can try to get a smaller offset; then minimize it completely by adjusting the lower resistors on each pair, you should get below a mV. Note that the JFETs are dual, and if you swap which half is used as the first and second JFET, you change the sign of any leftover DC offset; it's better to have such offset on both balanced lines the same sign so it's mostly common mode. Also, hifizen pointed out that some amplifiers such as Aleph-X should be AC coupled to this kind of buffer so current is not sent back into the buffer in case of DC offset in the Aleph-X; so maybe 10 uF for DC blocking, but I would put it on the amplifier side as it depends on what you are driving.
IMPORTANT: You cannot use a potentiometer or existing attenuator for R4, as the attenuation you'll get is no good. The curve needs to be logarithmic but more so than standard log pots; they won't give you a good result. You need a blank rotary switch (cheapest acceptable I found is Electroswitch C7D0223N from digikey). For the resistors I also used Roderstein MK3 from percyaudio. The values are given in the spreadsheet attenuator.xls. Column R' gives the closest actual resistances you can get to minimize the difference in attenuation between this and the optimal (resistors in column R). These are for a 24 position switch. For a 23 position, skip the last 1.96R resistor. The calculation takes into account that the 300R filter resistors and 500K (I used 511K) gate resistors are also part of the voltage divider volume control along with the 1K and the attenuator. What is NOT taken into account, however, is the output impedance of the CS43122, as that is not given in the datasheet and due to the switched capacitor output of this DAC I'm not sure it's a meaningful measure (that's why they only specify limits on the load). I don't think that will have any significant effect, so the resistances should make a properly behaving attenuator.
The Step column in decibels must be credited to the Goldpoint website, so I figure they know what a proper attenuation curve should look like. The reason that the attenuation column doesn't start at zero (max volume) but instead a bit lower is that even when R4 is open (infinite resistance), the gate resistors are parallel with it and limit the maximum possible volume. The voltages are given peak-to-peak. The input is assumed 7.3 V, because when I tested with a multimeter, I got about 2.5 rms on a 60 Hz sine (with the old buffer), which gives about 7 V peak-to-peak, indicating that what someone said in another thread that they must have meant 1.33*common mode instead of 1.33*VREF is mistaken, or I measured wrong (doesn't affect the resistance calculation anyway). Higher swing voltage than the power supply is possible since the output is capacitor switched.
It's hard to see. First I suggest you scrub the flux off with warm alcohol and a stiff brush (not metal of course), and then you can rinse with warm water before the alcohol dries out. Get a sharp pointed instrument such as a needle-nosed tweezers and scrape between every pair of adjacent solder joints to make sure there are no bridges nor any lodged solder particles, which can sometimes cause a short.
I finally got the attenuator switch. I didn't realize how big it was. It's 2" in diameter, and when I add the resistors it will be even bigger. jwb, do you think that the parasitic capacitance of the switch would be a problem for the DAC? I don't know what order of magnitude the capacitance of a rotary switch is (nothing in the datasheet, of course), and whether the series resistors before it affect the issue.
Prune,
I'm very glad you pointed out the revision change of the CS8420. I recently ordered a CS43122 and a CS8420 from newark and noticed the price went up to around $17 each compared to around $13 each. I wonder why..
Anyway, I'm wondering if newark will ship me the new revision. On their site, it said the CS8420 is on back order, so I'm wondering if they'll get the new revision. If I do, will I have to change the resistor and capacitor of the filter input?
Thanks.
I'm very glad you pointed out the revision change of the CS8420. I recently ordered a CS43122 and a CS8420 from newark and noticed the price went up to around $17 each compared to around $13 each. I wonder why..
Anyway, I'm wondering if newark will ship me the new revision. On their site, it said the CS8420 is on back order, so I'm wondering if they'll get the new revision. If I do, will I have to change the resistor and capacitor of the filter input?
Thanks.
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