Why would one use a mix of BF244 and BF245 devices? They are very much the same.
Be aware: the pinout is NOT the same!
http://www.farnell.com/datasheets/42147.pdf
Peter
Be aware: the pinout is NOT the same!
http://www.farnell.com/datasheets/42147.pdf
Peter
To the best of my knowledge, BF244 and BF245 are the same silicon, only different pinout.
I've used BF245C's to cascode BF245A's which works great for ~0.5...1.5mA CCS... still you need a source resistor for a clearly defined current. The A at ~1mA was choosen for mimimum tempco and low voltage drop, and the C for max cascode voltage.
- Klaus
I've used BF245C's to cascode BF245A's which works great for ~0.5...1.5mA CCS... still you need a source resistor for a clearly defined current. The A at ~1mA was choosen for mimimum tempco and low voltage drop, and the C for max cascode voltage.
- Klaus
Hello, If you are using a cascoded J-FET current source the Idss of the Upper fet should be slightly greater than the Lower fet so as to properly Bias the Lower fet. In addition this TI app note on Pg.11 shown is jfet casscode http://focus.ti.com/apps/docs/techdocsabstract.tsp?appId=1&abstractName=sboa046
Also this EDN article is a very good read on the subject. http://www.edn.com/article/CA6330095.html
I have used this type of current source a lot and they work great and can give isolation greater than 120 dB if enough voltage drop is available to properly Bias the FET’s . You may have noticed that this type is also used in my Cascoded output stage (Post#51)
While these work great I am considering moving over to a Cascoded BJT Current source as the Jfets current change quite a lot with tempo and this causes DC offset to be > than it should be. I am employing these types of J-FET current sources thought the Amplifier this output stage is used. The Problematic current source is the one for the LTP as these changes most greatly influences the DC offset. In my application of the Cascoded output stage referenced to in post#51 the feedback includes the Output stage at the moment, however due the low output impedance of this Cascoded output stage I am going to try operating it outside the LOOP.
Peter!
The DC offset issue you are having is best solved using complementary current mirrors with a common Bias current generator. Attached is a Stand alone version of my cascoded output stage intended to be used as a Unity gain Line/Headphone Driver. Provisions are included for DC offset adjustment you could upscale this paying attention to jfet voltage limitations (Again another reason I am considering going the Cascoded BJT way.
Also this EDN article is a very good read on the subject. http://www.edn.com/article/CA6330095.html
I have used this type of current source a lot and they work great and can give isolation greater than 120 dB if enough voltage drop is available to properly Bias the FET’s . You may have noticed that this type is also used in my Cascoded output stage (Post#51)
While these work great I am considering moving over to a Cascoded BJT Current source as the Jfets current change quite a lot with tempo and this causes DC offset to be > than it should be. I am employing these types of J-FET current sources thought the Amplifier this output stage is used. The Problematic current source is the one for the LTP as these changes most greatly influences the DC offset. In my application of the Cascoded output stage referenced to in post#51 the feedback includes the Output stage at the moment, however due the low output impedance of this Cascoded output stage I am going to try operating it outside the LOOP.
Peter!
The DC offset issue you are having is best solved using complementary current mirrors with a common Bias current generator. Attached is a Stand alone version of my cascoded output stage intended to be used as a Unity gain Line/Headphone Driver. Provisions are included for DC offset adjustment you could upscale this paying attention to jfet voltage limitations (Again another reason I am considering going the Cascoded BJT way.
Hi
Here is a good application note on CCS. This paper part 1 and part 2 by Mr. Borbely is a must read if you like
J-fets. Basically you want the cascade transistor to have a larger Vgs so that the source transistor Vds is greater than Vgs or the source fet will not operate in the saturation region. The choice is whether it is more economic to use a single fet CCS and whether it is worth it for the reduction of output conductance to cascade. As for Id variation w/temperature, refer to the transfer characteristics and choose Id at the zero temp coefficient Q-point. There is a special place in my heart for J-fets.
They can be very useful.
Here is a good application note on CCS. This paper part 1 and part 2 by Mr. Borbely is a must read if you like
J-fets. Basically you want the cascade transistor to have a larger Vgs so that the source transistor Vds is greater than Vgs or the source fet will not operate in the saturation region. The choice is whether it is more economic to use a single fet CCS and whether it is worth it for the reduction of output conductance to cascade. As for Id variation w/temperature, refer to the transfer characteristics and choose Id at the zero temp coefficient Q-point. There is a special place in my heart for J-fets.
They can be very useful.
Thank you all for the very valuable contributions!! Also very interesting articles you have mentioned. A lot of reading to be done I’m afraid…..
Klaus and Philip, nice to see you back here!
This is what I tried yesterday. Instead of the FET CCS which bias the LM4041/TL431, I used a fixed resistor for simplicity. DC drift is the best of all complementary CCS I have tried so far. The strong point is that these LM4041 and TL431 CCS have feedback and low TC.
I tried a common CCS with current mirrors, but that was not good enough to give the desired DC stability. Did however not try the double mirrors. When you catch one of the mirror transistors with your fingers, DC at the output immediately starts drifting away.
To have two CCS in series is like two Constant Voltage Sources in parallel, always problematic.
Peter
Klaus and Philip, nice to see you back here!
An externally hosted image should be here but it was not working when we last tested it.
This is what I tried yesterday. Instead of the FET CCS which bias the LM4041/TL431, I used a fixed resistor for simplicity. DC drift is the best of all complementary CCS I have tried so far. The strong point is that these LM4041 and TL431 CCS have feedback and low TC.
I tried a common CCS with current mirrors, but that was not good enough to give the desired DC stability. Did however not try the double mirrors. When you catch one of the mirror transistors with your fingers, DC at the output immediately starts drifting away.
To have two CCS in series is like two Constant Voltage Sources in parallel, always problematic.
Peter
Hi
Thanks for the Zero tempo operating tip. I arrived at the same conclusion, however for the Complete Amplifier once the DC offset is set to 0 the Amp Uncased sitting on the Bench will drift about -1 to +3 mV after 1 Hour of operation. It will stay below 5 mV after 8 Hours of operation however if large air currents are continuously circulating then DC can drift up to +25 mV. I think that once cased up this should be again under 5 mV over time and thus not a Problem. While the Output stage is inside the overall feedback loop there is only about 12 dB of Neg feedback at 1KHz. The feedback Loop contains a Cap and pot to add Bass Boost. When the Bass Boost is Full on the Amount of feed back is reduced to about 2 dB at DC. it is in this position that the thermals were an issue.
I have this working good now with only one or two minor complaints one i believe may be an issue with the Vbe Multiplier i use to set the Icq. if the Bias is set to more than 50 mV across the 1.1 Ohm output transistor Emitter resistors instability starts and is excited by probing the Base of the pre driver Transistors< however if set for under 40 mV the instability is completely Gone and probing in this area causes no instability, However i am not comfortable with an amp that can be adjusted into instability so im thinking different pot value or Divider values on the Vbe Multiplier so as to prevent adjustment greater than 40 mV however this all could then require pre-screening of transistors and such.
As Peter noted this type of Topology is hard to get stable and requires more work that one would initially suspect to obtain this, However once working the performance and sound quality are superb so i think this is a topology, That with further refinement could be the Output stage of one's Dreams
Thanks for the Zero tempo operating tip. I arrived at the same conclusion, however for the Complete Amplifier once the DC offset is set to 0 the Amp Uncased sitting on the Bench will drift about -1 to +3 mV after 1 Hour of operation. It will stay below 5 mV after 8 Hours of operation however if large air currents are continuously circulating then DC can drift up to +25 mV. I think that once cased up this should be again under 5 mV over time and thus not a Problem. While the Output stage is inside the overall feedback loop there is only about 12 dB of Neg feedback at 1KHz. The feedback Loop contains a Cap and pot to add Bass Boost. When the Bass Boost is Full on the Amount of feed back is reduced to about 2 dB at DC. it is in this position that the thermals were an issue.
I have this working good now with only one or two minor complaints one i believe may be an issue with the Vbe Multiplier i use to set the Icq. if the Bias is set to more than 50 mV across the 1.1 Ohm output transistor Emitter resistors instability starts and is excited by probing the Base of the pre driver Transistors< however if set for under 40 mV the instability is completely Gone and probing in this area causes no instability, However i am not comfortable with an amp that can be adjusted into instability so im thinking different pot value or Divider values on the Vbe Multiplier so as to prevent adjustment greater than 40 mV however this all could then require pre-screening of transistors and such.
As Peter noted this type of Topology is hard to get stable and requires more work that one would initially suspect to obtain this, However once working the performance and sound quality are superb so i think this is a topology, That with further refinement could be the Output stage of one's Dreams
i gather you replaced the diode stack with a Vbe multiplier..... did you put at least a 1uf cap across it? the oscillation could be from the bias voltage collapsing when the transistor begins conducting, and since the base bias for the Vbe multiplier transistpr collapses, the transistor reduces conduction and the voltage goes back up and the cycle begins again.
" i gather you replaced the diode stack with a Vbe multiplier..... did you put at least a 1uf cap across it? the oscillation could be from the bias voltage collapsing when the transistor begins conducting, and since the base bias for the Vbe multiplier transistpr collapses, the transistor reduces conduction and the voltage goes back up and the cycle begins again."
Thanks
I never used a diode stack in my version always a Vbe Multiplier. Yes a cap is placed from C to E on the Vbe however it is 0.1uF not 1uF.
Thanks
I never used a diode stack in my version always a Vbe Multiplier. Yes a cap is placed from C to E on the Vbe however it is 0.1uF not 1uF.
" I can suppose variant of cascode replacement of pair npn transistors. Using of MOS power transistors is preferred because its SOA is larger and output impedance much higher. First MOS transistor must be ordinary. Second - logic level. "
Replacing Mosfets ith BJT's is not my Cup of Tea. I am one of them that actually Dislike the sound of Mosfets, Moreover this has already Been done but with only one stage as opposed to Three stages we are talking about See http://www.amb.org/audio/beta22/
Replacing Mosfets ith BJT's is not my Cup of Tea. I am one of them that actually Dislike the sound of Mosfets, Moreover this has already Been done but with only one stage as opposed to Three stages we are talking about See http://www.amb.org/audio/beta22/
There is a 47uF capacitor across the diodes.
I did some research to get standing current as constant as possible. Especially because the triple is know for its thermal runaway. Tried Vbe multipliers and diode solutions. But by far the best way is to use stacked diodes (5 in my case) mounted on top of one of the power transistors. The picture shows how this can be made with a crimp terminal ring, 1N4148 diodes and some two part epoxy resin adhesive. The results are great! After power-up, within 20 seconds the final standing current is reached, and it remains stable within 10% during operation.
Peter
An externally hosted image should be here but it was not working when we last tested it.
diode stacks work. what's the capacitance between the diodes and the lug? or do you possibly have a short between one of the diodes and the lug? i've seen oscillation caused by a bias transistor and a heat sink clip shorting together. this happened regularly on an amplifier production line, so i saw it often enough for it to stick in my mind....
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