How are you handling the fact that the dac requires offset binary and you have got Signed Magnitude?
Does photo 9 not show what you get if you feed in SM instead of OB?
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Take a look at post 6116...:
Ecdesigns wrote:
With conventional (R2R / multibit) D/A converters all bits flip over simultaneously at the signal zero crossing. This produces both, switching noise and bit errors.
Our auditory system seems to be highly sensitive to everything that happens around these zero crossings. Now you know why class A amplifiers make a lot of sense as these will reduce but never fix problems around zero crossings and why SE amplifiers -can- sound so musical and involving as these reproduce zero crossings so accurately like no other amp can. The speakers are no exception either, problems, problems.
But lets concentrate on the DAC first. What could cause problems around zero crossings? all bits flipping over at the same time, just at most critical point in the audio signal.
1000000000000000 -> 0111111111111111, we have 16 bits flipping over simultaneously around the zero crossing!
This problem can be fixed if we use a signed magnitude DAC. As the name implies we have a sign bit (positive or negative) indicating the polarity and magnitude information (number) that, well determines the signal magnitude.
And what's so different about this approach?
With signed magnitude we usually have two identical DACs. One handles the positive signal halve only, the other handles the negative signal half only.
Now we can step away from the zero crossing with small steps in both directions like this:
Signal rises from zero crossing to plus, 000000000000000 -> 000000000000001 -> 000000000000010 and so on. L channel never goes below 000000000000000, we have only one bit flipping around the signal crossover, positive DAC is working, negative DAC takes a break.
Signal drops from zero crossing to minus, 111111111111111 -> 111111111111110 -> 111111111111101 and so on. R channel never goes above 111111111111111, we have only one bit flipping around the signal crossover. negative DAC is working, positive DAC takes a break.
MSB now becomes the sign bit that controls the polarity and no longer shows up in the data (magnitude) of both DACs. So we have a spare (extra) bit where MSB used to be. Now we can also double the resolution.
The outputs of both DACs are connected together.
Some examples of signed magnitude D/A converters are the Soekris DAC and the PCM1704 just to name a few of many.
The TDA1541A has two identical DACs that are usually used for L and R channel. But what if we used both channels to construct a signed magnitude mono DAC with it? We would need two TDA1541A chips as we need 4 DACs in total now. We end up with a 17 bit dual mono TDA1541A signed magnitude DAC, full scale current doubles to 8mA and resolution is doubled to 17 bits. Now this would be a very nice project for two (double crown) TDA1541A chips.
All we need to do is design a decoder that moves some bits around so we end up with output signals DOL- and DOL+ for TDA1541A #1 and DOR- and DOR+ for TDA1541A #2.
We could use a FPGA or ASIC, however, the nasty thing here is that we need to reduce (switching) noise to lowest practical level and that's going to be extremely difficult with these LSI chips that produce very strong interference. Even a tiny PAL (Programmable Array Logic) produces massive switching noise and draws a lot of current.
So there is little other option then building a decoder from a handful of discrete logic so we only use and connect those logic building blocks we need and we can locally decouple all these logic building blocks until switching noise is as low as it gets. Current consumption is also absolute minimum this way.
IF we insist using a noisy ASIC or CPU we have to ensure that the D/A converter is -completely- shielded (EMI included) from this switching noise, I wish you good luck with that.
Back to the Decoder circuit. I attached a schematic of a decoder I designed for this experiment, it is based on the protocol converter I posted earlier. It looks complicated but it is basically as simple as it gets.
We need to do a few things, sample and hold the MSBs, then loose the LSBs from the serial data that goes into the TDA1541A chips. Mix MSB and data signals together so we get dedicated data signals for each TDA1541A.
We know that the MSB are located immediately after a WS change (I use Left justified format!). So we need to create a trigger signal right at the center of these MSBs. We need 0.5 bit delay for that and that's provided by U1. We need to keep the Left MSB with the Left data and the Right MSB with the right data. So we have to invert the 0.5 bit delay signal for one channel. U4 and U5 sample and hold the MSB for each channel, we use these sampled MSBs in the decoder stage.
Loose the MSB, easier said then done as we can't easily shift the serial data to the left unless we add some more shift registers.
Instead I delayed the window that determines when the output signals are generated in relation to WS. By delaying the window signal by one bit I basically removed the MSBs from the serial bit stream, after I have sampled the MSBs of course.
The output of U2 provides a 1 bit delay and the delayed signal goes to the window generator built around counter U6 and NOR gate U17.
U3 lines up the left channel data so the bits are valid on the falling edge of BCKI (TDA1541A clocks on the falling edge of BCK when configured in the simultaneous mode).
U7 ... U10 line up the Right channel data with the Left channel data so both can be clocked out simultaneously.
U16 gates the bit clock so we have a 16 bit clock burst at just the right time. The window signal enables and disables the continuous BCKI signal.
U13 B and D do the same for the serial data, creating 16 bit data bursts at just the right moment.
U13A, U14, U13C and U15 form a simple AND / OR decoder that extracts DOL-, DOL+, DOR-, and DOR+ signals from the serial data streams.
People who need to have I2S input will have to add some more logic as MSB is shifted one bit to the right (with respect to WS) and both channels are swapped.
What we have to do now is adding one extra D flip-flops to sample the MSBs one and a half bit after a WS change (1.5 bit delay) and a 2 bit delay to drive the window generator so we still loose the MSB. DOL becomes DOR and DOR becomes DOL (swap channels) and we are ready to use I2S input signal.
Second picture shows the timing diagram. We can see that the whole window is shifted one bit to the right compared to the protocol converter timing diagram.
Third schematic shows the TDA1541A section. We need +4mA bias current for biasing two converters. This can be done using a 1K1 resistor between outputs and +5V. I try to avoid a CCS whenever possible as these are -very- nasty circuits that often result in grainy fatiguing sound. I traced this back to the non-linear impedance that varies with frequency, adding a shunt resistor across the CCS can improve things a bit by linearising the impedance.
The simple CCS we see in many schematics are not very precise and for this application we need a high precision CCS with very large bandwidth and superb impedance linearity. This usually translates to complex analogue circuits that in turn introduce new problems.
The full scale current has doubled to 8mA so the passive I/V resistor value has to be reduced to 75 Ohms. We get approx. 560mVpp output (1K1 is in parallel with 75R for ac). This lower output impedance comes in handy when we like to drive a step up transformer or a TVC with a gain tap.
A shorter explanation:
You use two TDA1541A (A and B)to make one signed magnitude DAC , both operating in simultaneous mode.
The data stream should be 17 bits long, but you take away MSB. The circuit samples the MSB and use it to determine which DAC gets the 16 bits after the MSB.
When MSB is 1 , DAC A gets the data , when MSB is 0 , DAC B gets the data and the outputs of DAC A and B is connected . This way DAC A only processes the positive part of the audio and DAC B processes the negative.
Voila a 17 bit signed magnitude DAC
Maybe now a little closer to a solution.
I found out, that if I adjusted my Wave generator to exactly the same frequency in R and L channel I got the result in pic. 21
Pretty close to what it should be, right?
It dosent matter what the level is in the other channel, it dose not alter the audio out.
If I alter the frequency so they are different in the two channels it all goes wacko.
And if I completely mute the other channel (no data and therefore no MSB in that channel) the result is as in pic.22
I think I can conclude, that the MSB from the other channel affects the channel I am measuring. So here is what we should be looking after.
I tried to swap the outputs from the two FF in U21 so NML became NMR and vice versa, hoping, with little confidence, that this was the problem, but that just worsened the case.
When I looked at the schematic again I was wandering if the detection of MSB 's presence is wrong as it is taken from the unaltered data stream (L first then R), so the timing of the MSB detection is not right??
I found out, that if I adjusted my Wave generator to exactly the same frequency in R and L channel I got the result in pic. 21
Pretty close to what it should be, right?
It dosent matter what the level is in the other channel, it dose not alter the audio out.
If I alter the frequency so they are different in the two channels it all goes wacko.
And if I completely mute the other channel (no data and therefore no MSB in that channel) the result is as in pic.22
I think I can conclude, that the MSB from the other channel affects the channel I am measuring. So here is what we should be looking after.
I tried to swap the outputs from the two FF in U21 so NML became NMR and vice versa, hoping, with little confidence, that this was the problem, but that just worsened the case.
When I looked at the schematic again I was wandering if the detection of MSB 's presence is wrong as it is taken from the unaltered data stream (L first then R), so the timing of the MSB detection is not right??
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Great findings Kolby!
The 1 bit I2S delay should not be an issue though if I get your point right.
U1 and U2 are here to have the LE delayed for 1,5 bit so it's edge would sit right under the MSB. I saw the signal on my logic analyser - it was at the right spot, both straight and iverted after U12
Building the ultimate NOS DAC using TDA1541A
"In order to sample MSBs we need a 1.5 bit delay. Now we sample MSB half a BCK period after it has changed. This is provided by cascading flip flops . First one gives 0.5 bit delay and the second one flips over one BCK clock period later on 1.5 bit delay."
Hey John! I didn't know that you already launched your new system! Congratulations.
How the new MOS16 compare to the MOSAIC UV???
How do we know when the battery is needing of recharge? Or, do we get the charger plugged in all the time and we just power on-off?
What Toslink do you recommend?
Best wishes,
M.
How the new MOS16 compare to the MOSAIC UV???
How do we know when the battery is needing of recharge? Or, do we get the charger plugged in all the time and we just power on-off?
What Toslink do you recommend?
Best wishes,
M.
You are right, xaled, it is not the 1 bit delay.
In order to clean up the signals from the Sim. converter , I mounted and gates on the four ( DOL+ DOL- DOR+ DOR- ) data outputs and this means there are no data present outside the clk window.
Pic.23 shows DOR- before the and gate and Pic. 24 after. The other trace is the BCK01.
BUT!!!
Now I have moved even closer to a solution. I asked xaled if he could make some wav. files with only data for one channel. That he did and now it is obvious whats wrong.!
Pic . 25 shows LE and BCK01. See the clock starts shortly after the falling edge.
Pic. 26 shows DATA-R @ U6 pin 4 while playing a wav. file with only data in the right channel. Data starts just after the rising edge..
So it is the data from the wrong channel that is being clocked in.
How do we rectify this situation?
In order to clean up the signals from the Sim. converter , I mounted and gates on the four ( DOL+ DOL- DOR+ DOR- ) data outputs and this means there are no data present outside the clk window.
Pic.23 shows DOR- before the and gate and Pic. 24 after. The other trace is the BCK01.
BUT!!!
Now I have moved even closer to a solution. I asked xaled if he could make some wav. files with only data for one channel. That he did and now it is obvious whats wrong.!
Pic . 25 shows LE and BCK01. See the clock starts shortly after the falling edge.
Pic. 26 shows DATA-R @ U6 pin 4 while playing a wav. file with only data in the right channel. Data starts just after the rising edge..
So it is the data from the wrong channel that is being clocked in.
How do we rectify this situation?
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Hi koldby
The original signed magnitude decoder circuit was designed and tested for use with Left Justified input.
It was later modified for I2S by adding an extra 1 bit delay and swapping the channels.
Unfortunately the MSB's were left unchanged and that means that the L channel MSB is used for the Right channel data and vice versa.
LJ: WS=0 -> Right channel data, WS=1 -> Left channel data.
I2S: WS=0 -> Left channel data, WS=1 -> Right channel data.
If we look at the schematic for the I2S version MSB (R) is sampled on the rising edge of WS.
However, the Right channel data appears after the falling edge of WS.
This can be easily fixed by swapping the outputs 6 and 8 of the 74xx74 dual flip-flop U21.
The original signed magnitude decoder circuit was designed and tested for use with Left Justified input.
It was later modified for I2S by adding an extra 1 bit delay and swapping the channels.
Unfortunately the MSB's were left unchanged and that means that the L channel MSB is used for the Right channel data and vice versa.
LJ: WS=0 -> Right channel data, WS=1 -> Left channel data.
I2S: WS=0 -> Left channel data, WS=1 -> Right channel data.
If we look at the schematic for the I2S version MSB (R) is sampled on the rising edge of WS.
However, the Right channel data appears after the falling edge of WS.
This can be easily fixed by swapping the outputs 6 and 8 of the 74xx74 dual flip-flop U21.
Thanks John..
That was my first thought too.
This is from post 7054:
"I think I can conclude, that the MSB from the other channel affects the channel I am measuring. So here is what we should be looking after.
I tried to swap the outputs from the two FF in U21 so NML became NMR and vice versa, hoping, with little confidence, that this was the problem, but that just worsened the case.
When I looked at the schematic again I was wandering if the detection of MSB 's presence is wrong as it is taken from the unaltered data stream (L first then R), so the timing of the MSB detection is not right?? "
I might have made a bad solder or a short , so I will try that again.
But what about the test I made that showed that the right data is not there when the clk widow is ?
Is it just a matter of reassigning the right to left and vise versa?
Hi John,
Of course you were right, I must have made an error first time I tried to swap NML and NMR because now , after swapping again ( pin 6 of U21 connected to pin 12 of U14 and pin 8 of U21 connected to pin 4 of U14) the resul is as shown in the Pic.
Don't you think it would be a good idea to include and gates at the output, to avoid the unwanted data in DOL- and DOR- ?
Of course you were right, I must have made an error first time I tried to swap NML and NMR because now , after swapping again ( pin 6 of U21 connected to pin 12 of U14 and pin 8 of U21 connected to pin 4 of U14) the resul is as shown in the Pic.
Don't you think it would be a good idea to include and gates at the output, to avoid the unwanted data in DOL- and DOR- ?
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Now that kolby got the board running I will update the current version of the board to include fixes for identified issues.
There is the open question for the need of AND gates at the output, to avoid the unwanted data in DOL- and DOR-. I will include the gates if there will be no comments against them or a proposal for a better solution.
Including the gates and other improvements will require some rerouting on the board and this will take some time.
I also want to get the I2S to Sign board to be useful in a stackable mode to have a dual TDA1541 board stackable on top of it. I will also try to design the right TDA1541 single ended board. Any cooperation on this would be appreciated.
I'm only interested in SE mode, but I know that there is also interest in balanced mode.
Is there any advantage for balanced mode with signed magnitude TDA1541 and I/V transformers that provide balanced mode on the secondary side?
There is the open question for the need of AND gates at the output, to avoid the unwanted data in DOL- and DOR-. I will include the gates if there will be no comments against them or a proposal for a better solution.
Including the gates and other improvements will require some rerouting on the board and this will take some time.
I also want to get the I2S to Sign board to be useful in a stackable mode to have a dual TDA1541 board stackable on top of it. I will also try to design the right TDA1541 single ended board. Any cooperation on this would be appreciated.
I'm only interested in SE mode, but I know that there is also interest in balanced mode.
Is there any advantage for balanced mode with signed magnitude TDA1541 and I/V transformers that provide balanced mode on the secondary side?
Proof of concept?
Remember I posted a picture of a the spikes around zero crossing in post 6575?
That is the second pic shown. It is one TDA1541A fed by Johns (and ryanj's) I2S to simultaneous converter.
The first picture is two TDA1541A fed by Johns (and xaled's) signed magnitude converter.
See the spike is totally gone around zero crossing. The first is a little more noisy, but I think it is because I measure directly over the 75 Ohm I/V resistor with no amplification after.
Remember I posted a picture of a the spikes around zero crossing in post 6575?
That is the second pic shown. It is one TDA1541A fed by Johns (and ryanj's) I2S to simultaneous converter.
The first picture is two TDA1541A fed by Johns (and xaled's) signed magnitude converter.
See the spike is totally gone around zero crossing. The first is a little more noisy, but I think it is because I measure directly over the 75 Ohm I/V resistor with no amplification after.
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Maybe, but I use sowter transformers now.
You can just increase the current in the circuit. 16 mA is no problem.
But why would you use stacked TDA1541A if you plan to use an active I/V converter?
John,
First of all my deep respect for all the time you made available to feed this thread with your knowledge.
You are obviously very experienced in the digital domain getting most out of a DAC and you are not a fan of brick wall filters, smearing the signal in the time domain.
What I understood from your latest version made with a DAC of your own, is that you are using dac's in sign magnitude set up, driving tri state buffers, from a + and - supply, making that the output has no DC offset, very clever.
I went through quite a number of the postings in this thread, but reading all of them would take me ages.
So may be I'm mentioning that has been addressed before.
The point is that in your designs a number of Dac's are are shifted in time with the same sample,filling the gap in equal steps between the next fresh sample.
So with 44.1kHz and 4 Dac's, Dac 2-4 are each shifted in 3 consecutive steps of 1/(44.1kHz*4)sec from Dac 1.
This is supposed to sort 2 effects, first lowering the error contribution of each individual DAC and thus lowering noise and second have a better reconstruction of the original signal because of the interpolation in several small steps instead of 1 large step.
Just out of curiousity, I made an LTSpice model with 3 variants, see image below.
1: No time time shifting, but 4 16bits Dac's converting at the same time, thereby improving accuracy and reducing noise in green, called V(Nos)
2: 4 16 bits Dac's time shifted giving much smaller interpolation steps in blue, called V(Out1)
3: A 4 times oversampled signal, as a reference in red, called V(Out3)
I'm very well aware of the fact that simulating is one thing and listening has it's own dynamic's, but nevertheless, base on the sim I have a few points.
When reconstructing a signal wit a DAC, it will be multiplied in magnitude by a sin(x)/x, making that f.i a 19kHz signal will be attenuated by 2.8dB when reconstructing at 44,1kHz.
When interpolating with 4 time shifted samples, this 2.8dB can easily double to 6dB.
So FR with this type of interpolating will have an earlier roll off, not a big deal, but nevertheless.
Looking at the spectra below for non shifting versus shifting the samples gives the same advantage in correcting individual errors between Dac's.
So what remains is that the first, second and third super sonic spectra are attenuated a bit, but the fourth at 176kHz is again at full strength.
After this long introduction, a simple question: in this sim the advantage of time shifting didn't become obvious, so I'm just curious whether you have auditioned this setup to a version where no time shifting takes place with just 4 Dac's parallel in time.
Thanks in advance,
Hans
First of all my deep respect for all the time you made available to feed this thread with your knowledge.
You are obviously very experienced in the digital domain getting most out of a DAC and you are not a fan of brick wall filters, smearing the signal in the time domain.
What I understood from your latest version made with a DAC of your own, is that you are using dac's in sign magnitude set up, driving tri state buffers, from a + and - supply, making that the output has no DC offset, very clever.
I went through quite a number of the postings in this thread, but reading all of them would take me ages.
So may be I'm mentioning that has been addressed before.
The point is that in your designs a number of Dac's are are shifted in time with the same sample,filling the gap in equal steps between the next fresh sample.
So with 44.1kHz and 4 Dac's, Dac 2-4 are each shifted in 3 consecutive steps of 1/(44.1kHz*4)sec from Dac 1.
This is supposed to sort 2 effects, first lowering the error contribution of each individual DAC and thus lowering noise and second have a better reconstruction of the original signal because of the interpolation in several small steps instead of 1 large step.
Just out of curiousity, I made an LTSpice model with 3 variants, see image below.
1: No time time shifting, but 4 16bits Dac's converting at the same time, thereby improving accuracy and reducing noise in green, called V(Nos)
2: 4 16 bits Dac's time shifted giving much smaller interpolation steps in blue, called V(Out1)
3: A 4 times oversampled signal, as a reference in red, called V(Out3)
I'm very well aware of the fact that simulating is one thing and listening has it's own dynamic's, but nevertheless, base on the sim I have a few points.
When reconstructing a signal wit a DAC, it will be multiplied in magnitude by a sin(x)/x, making that f.i a 19kHz signal will be attenuated by 2.8dB when reconstructing at 44,1kHz.
When interpolating with 4 time shifted samples, this 2.8dB can easily double to 6dB.
So FR with this type of interpolating will have an earlier roll off, not a big deal, but nevertheless.
Looking at the spectra below for non shifting versus shifting the samples gives the same advantage in correcting individual errors between Dac's.
So what remains is that the first, second and third super sonic spectra are attenuated a bit, but the fourth at 176kHz is again at full strength.
After this long introduction, a simple question: in this sim the advantage of time shifting didn't become obvious, so I'm just curious whether you have auditioned this setup to a version where no time shifting takes place with just 4 Dac's parallel in time.
Thanks in advance,
Hans
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Yes that is my preferred way of making the I/V conversion now and it is easy to make it balanced too.
I really like the sound of the Sowter as it makes the listening impression much more like listening to analog . Not at all blurred or soft but very see-through and a top end totally free from aggressiveness IMHO.