Building the ultimate NOS DAC using TDA1541A

When you say standard pcm do you just mean I2S with the WS transition one BCLK later (say as used by the TDA1545A)? In which case just a flip flop to delay WS by one bit clock period would do it.

<edit> to go the other way, just put the FF in the data line :) Assuming you can tolerate a 1 bit delay...
 
Hi maravedis,



I compared grounded grid buffer vs lateral MOSFET in the MK7 and I am still using the lateral MOSFET buffer.

Tubes add a lot of "things" like: coloration, distortion, noise and microphonics that are not optimal for a circuit that should offer highest possible transparency.

Here is an example of plain valve base vs gel valve base:
Audio Vibration Isolation, part 9, Absorb-GEL dampers

I also had a lot of problems with microphonics when experimenting with tubes. It is almost impossible to eliminate feedback between speakers and the mechanical construction inside the tube when both are placed in the same room. Since there is electrical charge between metal parts inside the tube, the slightest mechanical movement or resonance translates to voltage fluctuations causing distortion.

Things get worse as volume setting is turned up. Possible solution is placing the tube circuit in a different room.

Tubes also require coupling caps and / or coupling (output) transformers. Highest transparency requires fully DC-coupled signal path.

The required HV supply also prevents all TDA1541A bit currents flowing back into the +5V supply.


Hi EC Designs -

I've built the DAC board using a design fairly close to your Mk VII schematic. At this time, I am using just a 470pF at pins 16,17 (have not done the DEM re-clock yet) For a source, I'm using a Teradak USB to I2S with the 2.82MHz clock as the bit clock at pin 2.
What I'm seeing now is a fairly high distortion on the output - around 3% with an 80KHz LPF applied (using an HP8903B to measure) Also, the FFT of the output shows many oddball distortion products at non-1KHz multiples.
The gate of the FET output is nulled to 0V so there shouldn't be any issue with that part of the output.

Any suggestion as to why the distortion might be this high?

Thanks,
Gary
 
update in listening tests

Hi All, an update:

Testing the Philips CD player with aikido output, (highly modified, in fact it's no more a normal CD player, now it has 3 chassi) versus a higly modified Mark Levinson N360S, the results are:

The overal 3D image and stages are bigger and wider with the Philips CD. Voices and high frequencies are more sweet and detailed, more natural, vastly more natural. No distorsion at any frequency. Dinamics are exceptional, bass are incredible well defined and fast. Hearing "Pirates of the Carribean" The dead man's chest, it is no more a fatiguing experience. All is well defined and clear, no more confused bass "sinthetized orquestra".

I'm using this equipment and A/B comparisons:

Preamp: modified Audioresearch Ref2.
Power amp: modified B&K mosfet amp.
Speakers: (modified crossover) Vienna Beethoven, the old ones.
Cables from both sources to preamp: VDH Thunderline.
Cables from preamp to power amp: Zu "Gaede".
Cables from power amp to speakers: VDH The Revelation.

So far, failing to do more changes, these are the results.
 
Hi regal,

But With the NK7 single mofset output what sort of THD is being meaured?

Grounded gate buffers can offer THD levels that are low enough to match TDA1541A THD of 0.0018% @ 0dB. Advantages of grounded gate buffers are low noise and large bandwidth up to transistor / FET Ft. The single MOSFET also offers excellent dynamic tracking properties.

However, typical speaker THD varies from approx. 1 ... 5% for midrange / tweeters and up to 10% for woofers. This distortion is added to the (ultra low) THD of the connected circuits. So one may doubt if a difference in THD between say 5.01% and 5.001% is still audible. Test tracks show that audio circuit THD exceeding 1% is just barely audible on good speakers.


Anyway, after years of trial and error, I noticed that circuit dynamic tracking properties have far more impact on perceived sound quality than low THD.

Two circuits with exactly the same THD and different dynamic tracking properties can still sound entirely different.
 
Are you using a coupling cap? I don't think you can run the MKVII without one if you are using the redbaron board? Check for DC offset.

Hi,

Thanks for taking the time to answer.
The DC offset has been nulled to 0V at the output. The output voltage is 2Vp. I've also tried a coupling cap, but no change. As indicated, the FFT on my Tek scope confirms the presence of harmonics. It's interesting to note that without any filters applied on my HP8903B (audio analyzer) the distortion is 4%. With a 80KHz LPF, it's about 3.2%. With a 30KHz LPF, it's down to 1.1%, indicating higher order harmonics - perhaps some odd non-linear mixing going on.

The PCB is my layout, but pretty much follows EC Designs MK VII schematic he posted here on this thread. I'm using good layout rules, the PCB was manufactured. Completely bypassed everywhere, local power filtering,etc. Using 1uF decoupling at underside directly to pins. For supply voltages, I'm using Salas shunt regulators. All pin voltages at nominal values. The input uses a Teralink (Teradak) X2 USB to I2S, and I'm getting perfect
non-distorted signals in at pins 1 & 2. (2.82MHz BCLK, 44.1KHz LE/Word CLK)

As I indicated, the only difference at this point is that I am using a 470pF at pins 16,17 instead of a DEM re-clocking scheme. (This is on a different PCB but not yet completed) I did scope at pins 16,17 and find the oscillator to be around 230KHz. However, I find it difficult to believe that using just this cap (in lieu of DEM reclocking) would cause the distortion to be that high. After all, most high end CD players used just this and got much lower distortion.

Has anyone else in the forum actually measured this circuit's distortion, or looked at the spectral content with an FFT? Otherwise, I must be losing me marbles because I do not see where the problem is.

Any suggestions or input on your experience would be appreciated. I was hoping to hear from Mr.Brown himself as his experience would be most beneficial, but any input is welcome!

:confused:

Thanks,
Gary
 
Effect of lpf of your scope suggests something between 30-80khz.

What do you see on the scope at digital silence?

Actually, it's the audio analyzer that has the LPF. I have not observed the level/distortion with no audio signal through the USB. But I will do this and let you know. I will also test with the scope in FFT mode to verify any signals or residuals with no USB signal present.

Gary
 
The (digital) sine you are testing with is not clipped? Perhaps you could try again and back off some 6dbFS

Hi, thanks for your input.
I generated the test signal in Audacity, it's a 1Vp signal at 1KHz. To play back, I'm using Winamp (no equalization or other funny stuff) So no matter where the volume (output) slider is, distortion is constant. Of course, at very low levels the signal becomes too low for the HP test system to read and distortion goes up.

I have a bit of a theory about this distortion, maybe someone can confirm this. Since we are not oversampling (using in NOS mode), the use of a 470pF DEM cap here is causing these problems. The operation of the last 6 bits must be synchronized through the DEM oscillator inputs using the reconstruction circuit as per EC Designs (DEM reclock) or what I am seeing will be the result (high distortion) Can anyone confirm this? Has anyone else tried this?

BTW - I am building a separate input, PLL and re-clock PCB to feed the DAC PCB with a DEM re-clock, but it isn't ready yet. This is designed to have less than 10ps jitter so will provide reliable signals.

Gary
 
Try to measure WITH usb signal, but a silent signal for testing.

That way, there will be bck, ws and data coming into the chip, but there will be no sound. Have a look what the output is like.

studiostevus - thanks, I will test this later today when I get into the shop and let you know what I find.

Please, have a look at my other last posting and tell me if that proposition makes sense.

Gary
 
Hi, thanks for your input.
I generated the test signal in Audacity, it's a 1Vp signal at 1KHz. To play back, I'm using Winamp (no equalization or other funny stuff) So no matter where the volume (output) slider is, distortion is constant. Of course, at very low levels the signal becomes too low for the HP test system to read and distortion goes up.

I have a bit of a theory about this distortion, maybe someone can confirm this. Since we are not oversampling (using in NOS mode), the use of a 470pF DEM cap here is causing these problems. The operation of the last 6 bits must be synchronized through the DEM oscillator inputs using the reconstruction circuit as per EC Designs (DEM reclock) or what I am seeing will be the result (high distortion) Can anyone confirm this? Has anyone else tried this?

BTW - I am building a separate input, PLL and re-clock PCB to feed the DAC PCB with a DEM re-clock, but it isn't ready yet. This is designed to have less than 10ps jitter so will provide reliable signals.

Gary


The TDA1541A is intended to operate with an asynchronous DEM clock, that's whats in the datasheet and in most if not all Philips produced implementations. If you use 1, 4 or 8fs data does not mater.

If the DEM is not oscillating on the other hand you are left with a 10bit dac and performance is as such.

The test signal you used, its dithered to 16bits? You can try ARTA ARTA Home it lets you generate a properly dithered sine at any desired level in real time.
 
The TDA1541A is intended to operate with an asynchronous DEM clock, that's whats in the datasheet and in most if not all Philips produced implementations. If you use 1, 4 or 8fs data does not mater.

If the DEM is not oscillating on the other hand you are left with a 10bit dac and performance is as such.

The test signal you used, its dithered to 16bits? You can try ARTA ARTA Home it lets you generate a properly dithered sine at any desired level in real time.

Hi,
If what you say is true - a 470pF cap across pins 16/17 considered an asynchronous clock oscillating at 230KHz? This is not any multiple of Fs. Are you saying that it could be at 1fs, 2.335fs, 8fs, or 8fs and it makes no difference?

Audacity does produce a 16bit, I KHz sine wave at fs = 44.1KHz. The signal generated can be selected for bits and sampling frequency.

However, I'll have a look at the ARTA.

Thank you,
Gary
 
When you say standard pcm do you just mean I2S with the WS transition one BCLK later (say as used by the TDA1545A)? In which case just a flip flop to delay WS by one bit clock period would do it.

<edit> to go the other way, just put the FF in the data line :) Assuming you can tolerate a 1 bit delay...

thanks for the reply, nope, its for converting 16bit 'philips i2s' from an old iriver to 32bit pcm able to be used by sabre. it can be changed to accept it directly via a change in the registers, but i need a temporary solution and prefer to be able to A/B with a solution using a CS async chip. I have made a portable lifepo4 powered sabre with balanced headphone amp and modified my iriver ihp120 (modified for 32gb compact flash card) to output coax spdif on mini lemo bnc as well as i2s direct from the UDA1380TT, i'm planning on using the PS audio hdmi balanced i2s protocol (home made pcbs) to handle driving a short mini hdmi cable to the sabre, but i would like to integrate a hardware conversion to pcm.

also the hdmi method allows me to run it either from the iriver battery without worrying so much about DC offset, or run it from the lesser used negative battery rail to help keep the battery a bit more balanced. i use a balance charger, so no worries there about battery health, but presently the current drain is far higher on the positive rail and i end up with a heap of charge left on the neg rail, due to the entire dac, most of the power supply, battery monitor/housekeeping/shutdown logic, spdif comparator and the positive rail of the IV/Headamp/buffer on that side and only the neg rail of the iv/headamp/buffer on the neg side.

so preferably smallish, which shouldnt be an issue and efficient with the possibility of running with very low idle current. i have the schematic for the hdmi and isolation, but the philips->32bit pcm i'm a bit stuck for ideas
 
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Hi,
If what you say is true - a 470pF cap across pins 16/17 considered an asynchronous clock oscillating at 230KHz? This is not any multiple of Fs. Are you saying that it could be at 1fs, 2.335fs, 8fs, or 8fs and it makes no difference?

Yes the DEM clock does not have to be integer related to anything. The TDA1541A will work for 1fs, 4fs or 8fs data with the DEM running at 230Khz.
 
Yes the DEM clock does not have to be integer related to anything. The TDA1541A will work for 1fs, 4fs or 8fs data with the DEM running at 230Khz.

Ok. It sounds like there is more than 1 view on how the TDA1541A could/should be configured with respect to DEM reclocking vs NOT reclocking. From your answer, it seems you are on the NOT reclocking side. So, are you using the SAA7220 chip in front of your DAC? Or is your TDA1541A in NOS mode?

Gary