Doesn't matter, changing Rg has exactly the same effect as Rf, of changing the open loop gain. If you look at the basic CFA model after breaking the feedback loop (and considering the feedback loop elements loading), Rf and Rg are in parallel and their combination is defining the open loop gain.
Pole splitting is off topic, but because you mentioned it, a CFA may get more bandwidth but definitely not more loop gain compared to a VFA. The amount of loop gain is set by the Bode's maximum feedback theorem, which doesn't make any assumptions about any feedback configuration. See for example http://ukacc.group.shef.ac.uk/proceedings/control2004/Papers/063.pdf
The extra bandwidth in a CFA boils down to the JC fetish with the open loop bandwidth, and argument that I despise. It is totally irrelevant from any audio or non-audio perspective.
Hi All. I was just wondering if somebody could please provide additional details about the current requirements of the VAS and the the output stage affects the VAS loading. I found this in the output stage section of Bob book. Located under Darlington Output stage. "If the VAS produces a swing of 40 V peak for a 100-W/8-W amplifier, it will have to swing 8 mA peak." I understand how the 20k and 5k VAS load is calculated but how us the 8mA calculated. I am currently build a amplifier that only has a Darlington Output stage and would like to know how to correctly calculate the VAS bias current so I'm able to drive the output stage given any beta drop that I may encounter.
Thanks.
I should have alao added.
I believe that the 8 ohm load would see about 3.54A at 100watts so if the gain was reduced to 1250 won't the drive requirements of the driver transistor be 2.8mA call it 3mA?
So we could set the VAS bias at say 5mA for some margin.
I also understand that the npn driver's current requirement is the only transistor that is limited by the VAS bias.
I can get 8mA but dividing the 40v peak by the reduced VAS load of 5k to get a result of 8mA but how does this relate to the current requirements of the driver transistors which is approximately 3mA.
And how does this relate to the actual VAS quiescent current.
Thanks.
I should have alao added.
I believe that the 8 ohm load would see about 3.54A at 100watts so if the gain was reduced to 1250 won't the drive requirements of the driver transistor be 2.8mA call it 3mA?
So we could set the VAS bias at say 5mA for some margin.
I also understand that the npn driver's current requirement is the only transistor that is limited by the VAS bias.
I can get 8mA but dividing the 40v peak by the reduced VAS load of 5k to get a result of 8mA but how does this relate to the current requirements of the driver transistors which is approximately 3mA.
And how does this relate to the actual VAS quiescent current.
Hi Stuart,
In the example you cite on page 266, we are discussing an amplifier that is designed to produce 100 watts into an 8-ohm load, which requires peak output voltage of 40 V. That will cause 5 A to flow. I then suggest considering what happens when that same amplifier is called upon to deliver that same 40-V peak into a 4-ohm load. A peak current of 10 A will then be required to flow. Given those high current flows, as a worst case I suggested that there might be beta droop causing the current gains of the driver and output transistors to be halved to 50 and 25, respectively. Under those conditions, the total current gain of the Darlington output stage would be only 1250. The output current of 10 A, when divided by the output stage current gain of 1250 results in 8 mA that must be supplied by the VAS. The point here is that 80% of the available current from a single-ended VAS biased at 10 mA is used up. This situation will likely increase VAS distortion.
Best regards,
Bob
Thanks Bob. I appreciate your input. I think that I understand for the most part how to get all those numbers. I didn't realise that you were now putting 40v across the load. I thought this was the peak voltage the VAS could deliver. So give the 40v peak is across the load I assume is it just a simple case of the 10A output that is required for driving the load a 4 ohms divided by the reduced gain of 1250. Which gives us the 8ohms. How the 8mA was calculated was what I was confused about.
Thanks again for your time and extra explanation.
Thanks again for your time and extra explanation.
Hi bob when it comes to VAS transistor with 20ma of idle current as we have discussed earlier to drive the MJE15032 so in order to drive the MJE15032 driver transistor the vas transistor needs to be relatively larger like 2sc5171 now here i have a doubt about the driving the capacitance of the 5171 from the previous stage. Looking at the datasheet the Cob of MJE15032 goes upto 100pf and 2sc5171 goes upto 16pf. So when we drive the MJE15032 with 20ma idle current from the Vas transistor so how much idle current to be in the previous stage of VAS transistor to handle the capacitance of 16pf? approx 3ma?
Although I am oversimplifying a bit, the key here is to use a triple output stage rather than a double output stage. Then you have a pre-driver EF driving the MJE15032 with relative ease. I typically use a TO126 for the VAS and pre-driver, a TO220 (like 15032) for the driver, and a TO264 for the outputs. In such a case, running the VAS at 10 mA is a good number, and does not create excessive dissipation in the VAS, especially in amplifiers with higher rail voltages. It is remarkable how much of an improvement in overall performance an output triple makes over an output double. The great Bart Locanthi discovered this and advocated this back in the late '60s. There is simply not enough current gain in an output double, especially under conditions of beta droop and driving high output current.
Cheers,
Bob
Which is the same as: To achieve lowest distortion, the RELATIVE current swing of VAS should be minimized. With 10mA bias the output impedance of a cascoded VAS is in the ballpark of several 100kOhms, promising a very high loop gain - as long as it is not loaded significantly by the following drivers.
Improving VAS linearity thus means minimizing load current swing - which explains the advantage of triple darlingtons over standard darlingtons. In my latFET amp the VAS current swing is about 100uApp at 1kHz and 40Vpp output, corresponding to +-0.5% current excursion around 10mA bias current. This results in accordingly low harmonic distortion.
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triple ef for all bjt design, but one could use a fet as a bjt ops driver and only need a 2 stage design. You do loose headroom as with any fet design. parasound HCA designs show examples. Of course these days finding power complementary fets is near impossible, so back to 3EF for ease of use. Exicon's are expensive.
You have typically discussed 100 watt amplifiers (8 Ω) and driving them into 4 Ω loads at almost 200 watts. If we are looking in the 50 watt range, 38 V rails, with no intention of doubling power into 4 Ω, how much advantage is there to a triple?
This is a general rule valid for all power classes discussed here. For example if the triple darlington increases the current gain by a factor of 100 compared to simple darlington, the VAS is loaded by an impedance 100x bigger than before. Consequently the voltage gain of the VAS may increase upto 100x, and so does the loop gain: With 100x of loop gain the neg feedback is much stiffer than before reducing THD and output impedance by 1-2 orders of magnitude.
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VAS gain equals (gm * Rx) where Rx is the equivalent load resistance of the entire small signal equivalent circuit
Using the SPICE models on the Cordell Audio website, we find that VAS_xitor_ro is 440K and VAS_load_ro is 31K. Combining 440K and 31K in parallel, we get
With an 8 ohm loudspeaker load and a 2EF output stage, each EF transistor operating at beta=50, OPS_2EF_rin = 20K
With the same 8 ohm loudspeaker load and a 3EF output stage, each EF transistor again operating at beta=50, OPS_3EF_rin = 1Meg
So we see that going from a 2EF output stage to a 3EF output stage, has increased VAS gain by a factor of (28.2 / 11.8) = 2.4 times. Not 100X, not even close to 100X.
The reason is that VAS gain is not determined solely by OPS input impedance.
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Rx = (VAS_xitor_ro // VAS_load_ro // OPS_rin)
Using the SPICE models on the Cordell Audio website, we find that VAS_xitor_ro is 440K and VAS_load_ro is 31K. Combining 440K and 31K in parallel, we get
VAS Gain = gm * (OPS_rin // 29K)
With an 8 ohm loudspeaker load and a 2EF output stage, each EF transistor operating at beta=50, OPS_2EF_rin = 20K
VAS Gain (2EF) = gm * (20K // 29K) = gm * 11.8K
With the same 8 ohm loudspeaker load and a 3EF output stage, each EF transistor again operating at beta=50, OPS_3EF_rin = 1Meg
VAS Gain (3EF) = gm * (1Meg // 29K) = gm * 28.2K
So we see that going from a 2EF output stage to a 3EF output stage, has increased VAS gain by a factor of (28.2 / 11.8) = 2.4 times. Not 100X, not even close to 100X.
The reason is that VAS gain is not determined solely by OPS input impedance.
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The load on the VAS includes the compensation capacitor and its own Cbc, which may even be dominating at HF. For the voltage gain of the VAS to increse by 100 that would mean the ordinary darlington impedance is 100 times less than the VAS output impedance but that's very unlikely to be the case - for instance a 4 ohm load driven by an darlington OS with gains of 200 per device looks like a 160k load. The current source for the VAS may be around 500k, so increasing the OS gain by a hundred will raise the impedance from 160k to 500k, not to 16M. At 1kHz a 100pF compensation cap is 1.6M anyway.
Any emitter resistor on the VAS will have a big effect on its output impedance and needs taking into account too.
If the OS devices are low gain (or poor linearity) then a triple OS definitely makes sense, but with modern devices its may not make much difference as the loading on the VAS is perhaps a mA or so.
The primary way to reduce VAS distortion is to cascade or add an emitter follower to it. Then there is no voltage swing on the first VAS device to display Early effect nor Cbc effects, and the primary VAS transistor can be made high gain since it doesn't have to be high voltage.
Any emitter resistor on the VAS will have a big effect on its output impedance and needs taking into account too.
If the OS devices are low gain (or poor linearity) then a triple OS definitely makes sense, but with modern devices its may not make much difference as the loading on the VAS is perhaps a mA or so.
The primary way to reduce VAS distortion is to cascade or add an emitter follower to it. Then there is no voltage swing on the first VAS device to display Early effect nor Cbc effects, and the primary VAS transistor can be made high gain since it doesn't have to be high voltage.
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As I was too lazy to do the calculations, I wrote "may" and "upto" 100x.
The improvement in reality might be much less, depending on the characterics of the darlington transistors. In case of my LatFETamp I measured 13mVpp swing across the 130R emitter resistance of the small voltage VAS cascode driver transistor. This yields about 40Vpp output - i.e. VAS voltage gain is about
40,000/13 = 3000 and the VAS impedance incl all loads is close to 500kOhm at 1kHz.
The improvement in reality might be much less, depending on the characterics of the darlington transistors. In case of my LatFETamp I measured 13mVpp swing across the 130R emitter resistance of the small voltage VAS cascode driver transistor. This yields about 40Vpp output - i.e. VAS voltage gain is about
40,000/13 = 3000 and the VAS impedance incl all loads is close to 500kOhm at 1kHz.
It's all relative. Between given source and load voltages and impedances, "more stages" gives the *possibility* of improved performance.
I like to count the number of current gain stages. For conventional amplifiers, 4 stages makes fairly ordinary performance. (Input diff-pair, single Vas, Darlington outputs) Using Darlington Vas -or- triple-stage outputs is the next step and "can" give 5X-10X lower THD.
(FWIW: my earliest fiddlings were with 3-stage amps of very modest THD; they were easy to "improve".)
As Mark says, at some point more-stages is not much better until topology is changed. To his point: cascoding the Vas would let the higher Z of a Triple start to show, and has other (Early) advantages, but higher rail loss.
And more stages is more poles to squeeze inside the stability criterion. Making things more complicated often makes you crazy.
You can get 0.005% using a double at 1kHz into 8 Ohms 100 Watts. The problem comes when the load dips in impedance and/or at HF - you quickly end up with doubly or triple that distortion. What you see are quite big distortion swings over frequency and power.
with a triple, distortion is essentially flat with load and in a good amp frequency. you do need more care with a triple - layout, controlling parasitics, decoupling - which is where a double of course is much, much more forgiving.
with a triple, distortion is essentially flat with load and in a good amp frequency. you do need more care with a triple - layout, controlling parasitics, decoupling - which is where a double of course is much, much more forgiving.
