Hello all and Happy New Year.
Bob,
I made some transient simulation with your DH220 modified amp to see transient distortion.
To do that I record the difference between the output and the delayed input multiplied by the gain.
Delay is approximatively the group delay of the amp at the signal frequency, here 1kHz, delay ~118ns. I tuned the delay and the gain to have the least RMS.
This is what I obtain :
Do you think what I did is relevant or for some reason a non sense ?
Distortion is mainly crossover distortion, and from my side I never had better crossover distortion with mosfet output while I have much better results with bjt output.
This is for example what I have with one of my scheme :
As I never made (and probably I am unable) to do so accurate measurements on mos amplifier, I would like to know if you see this kind and level of distortion or if it is a problem of mos model and a simulator artifact ?
Thank you and best regards,
Bob,
I made some transient simulation with your DH220 modified amp to see transient distortion.
To do that I record the difference between the output and the delayed input multiplied by the gain.
Delay is approximatively the group delay of the amp at the signal frequency, here 1kHz, delay ~118ns. I tuned the delay and the gain to have the least RMS.
This is what I obtain :
Do you think what I did is relevant or for some reason a non sense ?
Distortion is mainly crossover distortion, and from my side I never had better crossover distortion with mosfet output while I have much better results with bjt output.
This is for example what I have with one of my scheme :
As I never made (and probably I am unable) to do so accurate measurements on mos amplifier, I would like to know if you see this kind and level of distortion or if it is a problem of mos model and a simulator artifact ?
Thank you and best regards,
Last edited:
Hi David,
Thanks for posting this. Any idea who wrote? I couldn't find anything on it indicating who wrote it and where it came from (maybe part of a Ph.D. thesis from the late 70's or early 80's).
Cheers,
Bob
It could be a thesis. I found it poking around Google looking for just this.
Let me know what you think. Are the tests good. Suitable for quality models.
The print quality suggests it might be that old.
I'll see if I can find something on it.
Hi Bob.
I did some more poking around and found it came from this site.
::AEi Systems - Analytical HEAVY Lifting::
I haven't looked around this site yet but it looks rather interesting. There might some other good spice stuff here.
https://www.linkedin.com/in/charles-hymowitz-9aa6493
I did some more poking around and found it came from this site.
::AEi Systems - Analytical HEAVY Lifting::
I haven't looked around this site yet but it looks rather interesting. There might some other good spice stuff here.
https://www.linkedin.com/in/charles-hymowitz-9aa6493
Last edited:
Hello all and Happy New Year.
Bob,
I made some transient simulation with your DH220 modified amp to see transient distortion.
To do that I record the difference between the output and the delayed input multiplied by the gain.
Delay is approximatively the group delay of the amp at the signal frequency, here 1kHz, delay ~118ns. I tuned the delay and the gain to have the least RMS.
This is what I obtain :
Do you think what I did is relevant or for some reason a non sense ?
Distortion is mainly crossover distortion, and from my side I never had better crossover distortion with mosfet output while I have much better results with bjt output.
This is for example what I have with one of my scheme :
As I never made (and probably I am unable) to do so accurate measurements on mos amplifier, I would like to know if you see this kind and level of distortion or if it is a problem of mos model and a simulator artifact ?
Thank you and best regards,
I think the technique you describe is valid; not completely different from the way my distortion magnifier works in concept.
What is the THD-1 distortion level that your waveform represents, and what is the peak amplitude of the output signal (its hard for me to see)?
For reference, my THD-1 sim yields 0.0011% at 40 volts peak driving an 8-ohm load (100 watts).
Due to lower transconductance and associated transconductance droop in the crossover region, MOSFET amps will often have higher THD numbers all else remaining the same (e.g., same IPS and VAS, and same feedback loop gain and ULGF. Put another way, the open-loop distortion of the MOSFET output stage alone is often greater than that of a properly-biased BJT design.
Not sure what you are showing in the third picture.
Cheers,
Bob
I get 0.00108% at 15 V peak on 8 ohm.
It is the same simulation with my schematics (second picture).
THD 1k is at 0.000007% at 15V peak on 8ohm (0.0001% at 20k 15V peak 8 ohm))
Rms on the picture is 813nV which I'm not sure it is relevant.
What I wanted to say is that there are no trace of crossover distortion on my plot, but if I replace last bjt with mos and even if I get similar thd and rms, I always get a peak at crossover that I can't remove as with bjt. I don't know if it is a model problem or if it is the same in true life.
Best,
I assume you are referring to cascodes where the cascode bases are fed with the common-mode signal presented to the differential pair, such as using a buffered version of the tail voltage or a replica of the feedback signal?
I have used the replica feedback approach to drive the cascodes, and it works great. It is especially helpful when high-capacitance JFETs are used in the IPS, like the LSK389.
Can you direct us to the place where that quote came from?
Cheers,
Bob
I gradually corrected.Through iterations.
I think we all should reflect on how difficult it must be for you to rely on Google for translation. Thanks for trying and for your contributions.
Jan
You also find it difficult to understand me. In my language it is allowed to rearrange the sequence of words in the phrase and this permutation does not harm understanding. For you it may sound like the speech of Master Yoda for Luke Skywalker.
I bought Kolinummi's book from the Linear Audio website and I encourage others to buy it too. On page 200 he says
_
The complementary symmetric input stage topology makes it easier to create a symmetric VA-stage. In such a circuit, asymmetric input-stage loading can be accepted without increased distortion, and this topology is also superior in terms of offset voltage, input current, and PSRR.
One of his examples of this idea appears on page 194. Not wanting to upload copyrighted material, I have redrawn it by hand, and made some (very!) slight changes; thus it's not a copy. Trust me, the schematic below faithfully represents the essence of his example. Or if you don't trust me, open the book to page 194 and find all of the differences. Maybe you won't agree they are very slight (?)_
Attachments
copyright never protects ideas, circuit topology...
no need for slight differences in the "intellectual content" to avoid copyright - just redrawing it is sufficient
copyright is only about the the specific expression and exact mechanical/photographic/digital copying
and there is also the "fair use" doctrine where exact copies of "small" portions of copyright protected works for educational, noncommercial use are allowed
no need for slight differences in the "intellectual content" to avoid copyright - just redrawing it is sufficient
copyright is only about the the specific expression and exact mechanical/photographic/digital copying
and there is also the "fair use" doctrine where exact copies of "small" portions of copyright protected works for educational, noncommercial use are allowed
Last edited:
Hi Mark,
Always remember that there is more than one way to skin a cat. I'd have to say that matching all four devices for gain is a serious down side to that way of doing things. If you don't agree with that, then try doing it just once and you'll be a convert. Once matched, the performance can be quite high, but other circuits also achieve high performance without the belly ache involved with matching 2 pairs of complementary parts.
-Chris
Always remember that there is more than one way to skin a cat. I'd have to say that matching all four devices for gain is a serious down side to that way of doing things. If you don't agree with that, then try doing it just once and you'll be a convert. Once matched, the performance can be quite high, but other circuits also achieve high performance without the belly ache involved with matching 2 pairs of complementary parts.
-Chris
Interesting circuit.
This appears to be a folded cascode, so VAS signal current cannot exceed IPS signal current (unless I've overlooked a factor of 2 somewhere.
Not sure about the noise performance without simulation.
What biases the 4 LEDs? If it is current sources, they would seem to need to be very carefully matched. Also, it looks like the LEDs must be matched in forward voltage.
Cheers,
Bob