i'm not looking at the datasheets right now, but doesn't the bf862 have more transconductance and less capacitance than the lxk3xx or lsk4xx?
and you're make a good point, it MIGHT be good to move this topic to its own thread.
makes sense to me at least ...
like that's saying something ...
mlloyd1
and you're make a good point, it MIGHT be good to move this topic to its own thread.
makes sense to me at least ...
like that's saying something ...
mlloyd1
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Hello Bob,
I am not sure if that was pointed before, but I think that an error about the Bias Spreader Employing ThermalTrak transistors shoud be corrected before second edition was released
On page 306 chapter 14 read:
"The bias spreader arrangement of Figure 14.19a....... R1 and R3 control the proportion of temperature coefficient introduced by the output transistor temperature"
This is not correct, it should read " R2 and R3 control the proportion..."
The formula to calculate Sensitivity to the tracking diode TC Sttd = R2/R3+1 and that gives for figure 14.19a Sttd of 1.44 not 1.3.
That error will lead to chose, wrongly, R3 to be trim pot to set the bias, instead to chose R1.
Figure 14.19 b and c have the same mistake. Somehow Sttd for figure 14.18c was wrongly calculated as 1.8 instead 1.55.
Best regards
Damir
I am not sure if that was pointed before, but I think that an error about the Bias Spreader Employing ThermalTrak transistors shoud be corrected before second edition was released
On page 306 chapter 14 read:
"The bias spreader arrangement of Figure 14.19a....... R1 and R3 control the proportion of temperature coefficient introduced by the output transistor temperature"
This is not correct, it should read " R2 and R3 control the proportion..."
The formula to calculate Sensitivity to the tracking diode TC Sttd = R2/R3+1 and that gives for figure 14.19a Sttd of 1.44 not 1.3.
That error will lead to chose, wrongly, R3 to be trim pot to set the bias, instead to chose R1.
Figure 14.19 b and c have the same mistake. Somehow Sttd for figure 14.18c was wrongly calculated as 1.8 instead 1.55.
Best regards
Damir
Question on Bobs amplifier book
Hello Bob,
I have enjoyed your book very much, especially your elucidation on stability issues, the theory , simulation and meausurement.
My question relates to figure 12.7 page 253 in which you show your EC output stage and how to break the loop and measure the loop gain, how do you maintain the DC output condition to do the the measurement or am I missing something.
Regards
Arthur
Hello Bob,
I have enjoyed your book very much, especially your elucidation on stability issues, the theory , simulation and meausurement.
My question relates to figure 12.7 page 253 in which you show your EC output stage and how to break the loop and measure the loop gain, how do you maintain the DC output condition to do the the measurement or am I missing something.
Regards
Arthur
Bob, some time ago, I suggested you include in your next edition, a look at John Vanderkooy's "A Simple Reliable Power Amplifier with Minimal Component Count" AES E-Library A Simple Reliable Power Amplifier with Minimal Component Count
I now know Ed Cherry proposed it in 1968
"Amplifying Devices & Low-Pass Amplifier Design" - Cherry & Hooper, Wiley NY 1968
Fig14.26b pg891
He explains some of the advantages more recently in
"Ironing out distortion" Electronics World jul97
Indeed Great Guru Baxandall used a similar idea in some 1970's personal correspondence to explain the equivalence of CE & CC output stages
I now know Ed Cherry proposed it in 1968
"Amplifying Devices & Low-Pass Amplifier Design" - Cherry & Hooper, Wiley NY 1968
Fig14.26b pg891
He explains some of the advantages more recently in
"Ironing out distortion" Electronics World jul97
Indeed Great Guru Baxandall used a similar idea in some 1970's personal correspondence to explain the equivalence of CE & CC output stages
Hi Rick,
Not sure what the problem is. My LSK489 amp in the Linear Systems app note simulates at 0.017% THD-20 at 40V peak into 4 ohms (200W). Your schematic seems to have quite a few changes to it, so I'm not sure where the problem might be. Putting in the LSK389 or BF862, which have higher gm, likely may reduce the distortion, but cover up an underlying problem.
Sorry to be slow to answer these posts, but just got back from vacation and am digging out of about 100 emails and catching up on other stuff as well. I'll try to answer some of the other posts this week.
Cheers,
Bob
Hi ivanlukic,
Thanks for your interest in my book.
Unfortunately, due to numerous personal and professional distractions, I have not made as much progress on my second edition as hoped. It is so easy, at least for me, to underestimate the time it takes to do a task, and the other things that may intervene along the way. This all in spite of the fact that I have been retired for a year now.
I am currently hoping to publish the second edition in September of 2015, about a year from now.
For those of you who have pointed out errors and areas for improvement, I deeply appreciate that and have been keeping track of them. It is definitely not too late to provide more input.
Cheers,
Bob
Hello Bob,
You never confirmed or negated this. I would like to hear your opinion.
Best regards
Damir
Hi Damir,
I apologize for being slow to get back to you on this. I checked the book and I think you are right. I think also that I should have devoted a few more words to these explanations and double-checked that math. I should have also done a sanity check on the sensitivity numbers via simulation.
Thanks again for the heads-up.
Cheers,
Bob
Hi Arthur,
The loop that is being broken is from the output of the output stage to the error injection point at the junction of R5 and R6. This particular feedback path is not responsible for dc stability of the error-corrected output stage. By means of the various resistor networks, this path is mainly involved in feeding back the error between the signal at the output of the driver and the output of the output stage. I should have said a few more words there about this issue.
Cheers,
Bob
Hi kgrlee,
Thanks for pointing this out. I'll try to get a hold of some of these references and look into it. In addition to the nuts and bolts, I'm always interested in gathering more references for my chapters.
Cheers,
Bob
Hi Anistaerdt,
Not sure which kind of IM distortion you are referring to, SMPTE or 19+20kHz CCIF with spectral analysis.
However, your observation can certainly be true. High slew rate, in and of itself, does not necessarily lead to lower IM distortion, be it SMPTE or CCIF. However, it is true that amplifiers with insufficient slew rate may be likely to exhibit higher IM distortion on tests that include signals with significant slew rate.
Cheers,
Bob
Hi keantoken,
I assume that you are referring to the MOSFET push-pull EF output stage wingspead plot in Doug Self’s Figure 21.1, page 498 in his Sixth Edition.
To begin, and answer your question directly, I don't know of anyone, including myself, that has made a measured wingspread plot of a MOSFET output stage. This would probably be a good thing to do, and I honestly have not given much thought on how to do it. A good DSO and a triangle wave source in the right arrangement might facilitate it.
However, with regard to simulated wingspread of a MOSFET output stage, the one that appears in my book as Figure 11.12 on page 234 shows much better performance than the one in Self's book. There can be numerous reasons for this. Self is simulating lateral MOSFETs which, as I have pointed out, have lower transconductance than vertical MOSFETs, which I simulated in my Figure 11.12. Also, I cannot find any mention of at what bias level he conducted his wingspread. This of course is very important. I have always pointed out that MOSFETs perform better with a higher bias level, as is evident from my Figure 11.12.
Finally, he says nothing about what models are being used, and completely ignores the matter of low-current modeling of MOSFETs, which require something like the EKV model for accuracy, ESPCIALLY in the crossover region. He almost certainly used the simple square-law model that has a sharp discontinuity in transconductance at lower currents. This would of course lead to sharper changes in the wingspread he showed. No such sharp corners are evident in my wingspread, which was done with proper models.
Self's wingspread shows a minimum gain of 0.79 into an 8-ohm load, whereas mine, with a bias of 150mA shows a minimum of 0.94. At 250mA, where we have an even larger class A region, the gain minimum on my wingspread is 0.955. The use of vertical MOSFETs, proper bias, and proper models shows that MOSFETs perform quite well, in great contrast to what Self asserts.
It has always been the case that I have agreed that MOSFETs tend to have a bit less gain and have transconductance droop, all the way back to 1983, when I discussed my MOSFET power amplifier.
Self has always been a naysayer in regard to MOSFETs, and appears to be very biased against them. I doubt that he has ever built a MOSFET power amplifier, much less one wherein he tried with his considerable skills to get the best performance. His dismissive discussion of MOSFETs is only 7 pages in his whole book. A fair approach is to try to make the best performance of either technology when comparing them. This is what I tried to do in my book. I tried just as hard to make the best BJT designs as MOSFET designs. The BJT ThermalTrak discussion is a good example of that. ThermalTraks mitigate many of the dynamic thermal bias stability problems that can impair BJT performance. Pick your poison. Each technology has its own advantages and disadvantages. My belief is that the best approaches with each should be fairly presented so that the reader can make an informed choice with regard to which technology he or she chooses.
It is remarkable that Self did not reference any of my work on MOSFET amplifiers, which demonstrates very good performance with MOSFETs, going back to 1983. This seems to illustrate his lack of interest in discussing cases where good results have been achieved with MOSFETs. It is also notable that he says not a word about the very successful and well-regarded Hafler MOSFET amplifiers.
Note that in my 1983 MOSFET amplifier, I achieved below 0.001% THD at 20kHz. That amplifier biased a single pair of vertical MOSFETs at 150mA. The error correction provided about 20dB of distortion reduction at 20kHz. That means that without error correction this amplifier would have come in at about 0.01% THD-20, which is quite good. These are MEASURED results. The use of 2 pair at a total bias of 300mA would just about cut that number in half. Higher bias current would reduce the distortion still further, while increasing the size of the class A region.
Higher bias current in an audiophile amplifier is a good thing (as long as you don’t have a gm doubling constraint), as long as the heat sinks don’t get too hot, reliability is not compromised, and you are not obsessive about your electric bill. 300mA at +/-50V rails is only 30W. No big deal.
Cheers,
Bob
Per channel, plus power supply losses. So we'd probably be looking at about 70 W for a stereo amp in idle, which is still feasible, but a multichannel version with 5 or even 7 channels would run uncomfortably hot and rival a high-performance PC in power consumption.
Power is >0.20 € / kWh over here, btw.
Bob, why don't you check out these EKV models by Ian Hegglun:
LACAv8 - PAK2 devo
They are part of his article in Linear Audio. I tested them and they didn't match the datasheet. But then I realized the datasheet didn't match itself, so no wonder. I don't have access to Ian's article so I will try to contact him.
The VDMOS model in LTSpice does support subthreshold conduction now that Mike updated it. It is modeled a bit differently from EKV so I don't know which is more correct. However the EKV models show far less gate current than the VDMOS models, so I'm thinking the VDMOS with subthreshold parameters may be better.
LACAv8 - PAK2 devo
They are part of his article in Linear Audio. I tested them and they didn't match the datasheet. But then I realized the datasheet didn't match itself, so no wonder. I don't have access to Ian's article so I will try to contact him.
The VDMOS model in LTSpice does support subthreshold conduction now that Mike updated it. It is modeled a bit differently from EKV so I don't know which is more correct. However the EKV models show far less gate current than the VDMOS models, so I'm thinking the VDMOS with subthreshold parameters may be better.